Exploration of Nanometer Cognitive Reasoning Very Large Scale Integration (VLSI) Computer Architecures

Abstract

Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES)Air Force Research Laboratory/RITB 525 Brooks Road Rome NY 13441-4505 SPONSOR/MONITOR'S ACRONYM(S)AFRL/RI SPONSORING/MONITORING AGENCY REPORT NUMBER AFRL-RI-RS-TR-2012-134 DISTRIBUTION AVAILABILITY STATEMENTApproved for Public Release; Distribution Unlimited. PA# 88 ABW-2012-2306 Date Cleared: 16 Apr 2012 SUPPLEMENTARY NOTES ABSTRACTThe objectives of this work were to design, develop, and evaluate support for the design of low-power hardware computer architectures at the Very Large Scale Integration (VLSI) level. The objectives were realized by achieving complete design flow integration with commercial and open-source Electronic Design Automation tools. The design flow takes as inputs a high-level system-level architecture description, along with area, critical path delay, and power dissipation constraints. Based on the System on Chip architecture description and design constraints, the tools automatically generate synthesizable Hardware Descriptive Language (HDL) models, embedded memories, and custom components to implement the specified VLSI architecture. Simulation results showed significant improvement over previous approaches with respect to power dissipation and leakage reduction.