Application of Global Loops on ULSI Routing for DfY

Panitz, P.; Olbrich, M.; Koehl, J.; Barke, E.

doi:10.1109/icicdt.2006.1669409

Cited by 2 publications

(5 citation statements)

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“…According to [9] the MRHC has some disadvantages. In a single global loop connecting all pins at least a few pins have high source to sink delay.…”

Section: Routing Objectives and Extreme Solutionsmentioning

confidence: 98%

“…Whereas the minimal rectangular Steiner tree (MRST) is the wire length minimal solution to the wiring problem with R = 0 [7], a minimal rectangular Hamiltonian cycle (MRHC) was proposed as a fully robust (R = 1) wiring solution in [9]. It was shown that the minimal Hamiltonian cycle is a nearly optimal solution for the 2-edge-connected subgraph problem (2ECON) introduced by [5].…”

Section: Routing Objectives and Extreme Solutionsmentioning

confidence: 99%

“…It has also been applied to improve performance [8] and to reduce sensitivity to open faults and variation [6,1,9] in signal nets. [1] adds local loops into the wiring to increase the number of redundant vias.…”

Section: Introductionmentioning

confidence: 99%

“…This reduces the likelyhood of via opens. In [9] the application of a single global loop as wiring network is analyzed. Links are inserted into tree networks to reduce Aopens in [6].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Robust wiring networks for DfY considering timing constraints

Panitz¹,

Olbrich²,

Barke³

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.

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“…According to [9] the MRHC has some disadvantages. In a single global loop connecting all pins at least a few pins have high source to sink delay.…”

Section: Routing Objectives and Extreme Solutionsmentioning

confidence: 98%

Section: Routing Objectives and Extreme Solutionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…This reduces the likelyhood of via opens. In [9] the application of a single global loop as wiring network is analyzed. Links are inserted into tree networks to reduce Aopens in [6].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Robust wiring networks for DfY considering timing constraints

Panitz¹,

Olbrich²,

Barke³

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…We have applied an industrial tool to insert multi-cut via post detail routing . Also, local loops [11] and global loops [12] have been proposed to increase redundancy rates further.…”

Section: Global Routing and Detail Routing Overviewmentioning

confidence: 99%