Application of compact HCI model to prediction of process effect in 28FDSOI technology

Arfaoui, W.; Federspiel, X.; Bravaix, A.; Mora, P.; Cros, A.; Roy, D.

doi:10.1109/iirw.2014.7049513

Cited by 12 publications

(6 citation statements)

References 7 publications

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“…For high VDS condition, especially in peripherals such as EM and SCAN drivers, the electric field near drain side can generate electron/hole pair. Then, holes in p-channel LTPS TFTs are trapped into the gate insulator and grain boundaries, resulting in reducing Ion; this drainavalanche hot carrier (DAHC) effects is aggravated for short channel devices because of the increased drain field [16]- [19]. Fig.…”

Section: Reliability Of Short-channel Ltps Tftsmentioning

confidence: 99%

14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

Kim

Chu

Lee

et al. 2022

Symp Digest of Tech Papers

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This paper presents recent progress to scale down low‐temperature polysilicon (LTPS) TFT technologies in the extremely short‐channel length regime for AMOLED displays. Process integration of short‐channel gate and narrow‐width polysilicon into scaled equivalent gate‐oxide thickness (EOT), is explored, in conjunction with enhanced poly crystallization by reducing defect density‐of‐state (DOS) especially in the grain boundaries of the channel region. We obtain more than twice higher current drive (Ion) with significantly‐reduced parasitic gate capacitance, thereby enabling high‐performance high‐frequency panel operations. In addition to superior panel performance in scaled LTPS TFTs, reliable devices are attained, demonstrating robust device characteristics for negative‐bias instability (NBTI) and hot carrier injection (HCI) effects. Physics‐based analysis, based on experimental data and numerical device simulations, is performed to gain more insight in the TFT technologies.

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Section: Reliability Of Short-channel Ltps Tftsmentioning

confidence: 99%

14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

Kim

Chu

Lee

et al. 2022

Symp Digest of Tech Papers

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“…A simplified version of the energy-driven AGE model is proposed in Ref. [30] as Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies http://dx.doi.org/10.5772/intechopen.68825…”

Section: An Energy-driven Age Modelmentioning

confidence: 99%

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

Lee¹

2018

Very-Large-Scale Integration

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The historical evolution of hot carrier degradation mechanisms and their physical models are reviewed and an energy-driven hot carrier aging model is verified that can reproduce 62-nm-gate-long hot carrier degradation of transistors through consistent aging-parameter extractions for circuit simulation. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the V GS ratio is emphasized during practical case studies on CMOS inverter chains and a dynamic random access memory (DRAM) word-line circuit. Negative bias temperature instability (NBTI) mechanisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) framework. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, ΔN it with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si-Hbondbreakageisalsoprovenby the quantifying R-D simulation. From this analysis, a low-pressure end-of-line (EOL) anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffusion of hydrogen from the gate regions and therefore prevents further breakage of Si-H bonds in the silicon-oxide interfaces.

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confidence: 99%

“…As L is scaled, pristine Ioff increases, however, off-stressed Ioff decreases. The short-channel LTPS TFT with controlled device/reliability characteristics[17], can reduce IGIDL by enhanced off-stress. The process methods of reducing polysilicon defects and increasing the generation life time (G) can reduce IGt (see equation(3) and Fig.3).…”

mentioning

confidence: 99%

5‐3: Experimental and Physics‐Based Analysis of Leakage Currents for LTPS TFTs in AMOLED Displays

Kim

Chu

et al. 2021

Symp Digest of Tech Papers

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This paper presents extremely‐low leakage technologies in low‐temperature polysilicon (LTPS) TFTs. Experimental and physics‐based analysis of leakage currents, emphasizing the effects of process technologies and device design, are described. Small‐geometry TFTs, controlled by optimal LTPS process, dramatically reduce off‐state leakage current (Ioff) by suppressing gate‐induced drain leakage (GIDL) and thermal generation currents, thus potentially offering lower frame rate operations by reducing IC clock power. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate the remarkable low‐Ioff experimental results as well as more‐than‐twice enhanced on‐state current (Ion) in optimized LTPS devices.

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Application of compact HCI model to prediction of process effect in 28FDSOI technology

Cited by 12 publications

References 7 publications

14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

5‐3: Experimental and Physics‐Based Analysis of Leakage Currents for LTPS TFTs in AMOLED Displays

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