Application-driven design automation for microprocessor design

Pyo, I.; Su, C.-L.; Huang, I.-J.; Pan, K.-R.; Koh, Y.; Tsui, C.-Y.; Chen, H.-T.; Cheng, G.; Liu, S.; Wu, S.; Despain, A.M.

doi:10.1109/dac.1992.227750

Cited by 10 publications

(3 citation statements)

References 14 publications

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“…Researchers have proposed to support the development of such systems by providing languages that allow the designer to quickly describe a customized architecture [Pyo et al , 1992;Park and Walker, 1988]. The research presented in our paper, on the other hand, is designed to support the development of arbitrary circuits, not just microprocessors.…”

Section: Related Workmentioning

confidence: 99%

A Synthesis Algorithm for Modular Design of Pipelined Circuits

Marinescu

Rinard

2000

VLSI: Systems on a Chip

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This paper presents a synthesis algorithm for pipelined circuits. Thc circuit is specified as a collection of independent, loosclycoupled modules connected by queues. The sYllthesis algorithm transfOrIns this asynchronous, modular specification iuto a synchronous, tightlycoupled, and fully pipelilled circuit in which queues are illlplelllented as finite buffers. Data is read frolll the buflers at the begining of each dock cycle, ncw values are cOlllputed, then the new results are written back into the buffers at the end of each dock cyde.We have illlplelIlented a prototype synthesizer that is capable of automatically gcneratillg synchronous, fully pipelined implelllcntatiollS of modular specifications. This paper presents experimental results from this synthesizer.

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Section: Related Workmentioning

confidence: 99%

A Synthesis Algorithm for Modular Design of Pipelined Circuits

Marinescu

Rinard

2000

VLSI: Systems on a Chip

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“…Whereas application specific integrated processors (ASIPs) [7]- [11] target specific application areas and achieve their optimization through a combination of instruction set selection/implementation and architectural variation, we have chosen a general purpose architecture with an invariant instruction set. We balance the performance Fig.…”

Section: Cpu Architecturementioning

confidence: 99%

Memory-CPU size optimization for embedded system designs

Shackleford

Yasuda

Okushi

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

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“…We have resynthesized various blocks on an industrial chip using LRAP (Logic Restructuring After Placement), a prototype program in the Application-Driven Automation System ADAS [18]. ADAS is capable of translating a high level instruction set description of a microprocessor into a layout representation.…”

Section: Introductionmentioning

confidence: 99%

Alleviating routing congestion by combining logic resynthesis and linear placement

Liu

Pan

Pedram

et al.

1993 European Conference on Design Automation With the European Event in ASIC Design

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We present a novel technique that combines logic resynthesis and linear placement in order to alleviate routing congestion in bit-sliced layout. In this approach, we restructure the logic using an intermediate placement solution and then adjust the placement to match the new logic structure. This ability to change logic structure during layout allows us to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been re-synthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared t o the original designs.

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Application-driven design automation for microprocessor design

Cited by 10 publications

References 14 publications

A Synthesis Algorithm for Modular Design of Pipelined Circuits

A Synthesis Algorithm for Modular Design of Pipelined Circuits

Memory-CPU size optimization for embedded system designs

Alleviating routing congestion by combining logic resynthesis and linear placement

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