Alleviating routing congestion by combining logic resynthesis and linear placement

Abstract

We present a novel technique that combines logic resynthesis and linear placement in order to alleviate routing congestion in bit-sliced layout. In this approach, we restructure the logic using an intermediate placement solution and then adjust the placement to match the new logic structure. This ability to change logic structure during layout allows us to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been re-synthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared t o the original designs.