Application-Aware Topology Reconfiguration for On-Chip Networks

Modarressi, Mehdi; Tavakkol, Arash; Sarbazi-Azad, Hamid

doi:10.1109/tvlsi.2010.2066586

Cited by 94 publications

(71 citation statements)

References 35 publications

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“…[16]. The area overhead of the proposed SCP-based NoC when implementing a 6 Â 6 mesh with 64-bit links and 8-flit buffers over a 64-bit conventional NoC is 7%, mainly caused by multiplexers and SCP registers.…”

Section: Trade-off Between Area and Performancementioning

confidence: 96%

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Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

2015

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Section: Trade-off Between Area and Performancementioning

confidence: 96%

“…The monitoring and adaption procedures can be either done by cores or by a special hardware unit in the NoC [29]. Many dynamic adaption methods target NoC topology by presenting fully reconfigurable topologies [10,[14][15][16]27] or buffers and virtual channels [30,31].…”

Section: Related Workmentioning

confidence: 99%

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

2015

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“…This register is set when the topology is constructed. In this work, we adopt the existing long link flow control and irregular topology deadlock avoidance (by using virtual channels) mechanisms introduced in [3]. In regular routers, packets are first buffered at each hop and then go through the router pipeline stages.…”

Section: Dark Silicon-aware Reconfigurable Nocmentioning

confidence: 99%

“…The proposed NoC provides virtual pipelined inter-core connections among active cores by bypassing dark cores to enable NoC to operate in the same way as the case when the cores are placed nearby. Although the physical distance of the cores is not changed, by bypassing routers considerable reduction in communication power and latency can be achieved, since the latency and power consumption of routers make significant contributions to the total NoC latency and power consumption [3]. In the following sections, we introduce and evaluate the proposed NoC architecture and design flow.…”

Section: Introductionmentioning

confidence: 99%

A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era

Modarressi

Sarbazi-Azad

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Core specialization is a promising solution to the dark silicon challenge. This approach trades off the cheaper silicon area with energy-efficiency by integrating a selection of many diverse application-specific cores into a single billiontransistor multicore chip. Each application then activates the subset of cores that best matches its processing requirements. These cores act as a customized application-specific CMP for the application. Such an arrangement of cores requires some special on-chip inter-core communication treatment to efficiently connect active cores. In this paper, we propose a reconfigurable networkon-chip that leverages the routers of the dark portion of the chip to customize the topology for the powered cores at any time. To this end, routers of the dark parts of the chip are used as bypass switches that can directly connect distant active nodes in the network. Our experimental results show considerable reduction in energy consumption and latency of on-chip communication.

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“…Since router delays can vary depending on congestion [1], [11], some prior research [12]- [16] has proposed pre-reservation of (parts of) the route to provide predictable and bounded delays. These works perform an offline computation of contention free routes, allowing flits 1 to bypass queues and arbiters at routers where there is no conflict between the routes of different flows.…”

Section: Introductionmentioning

confidence: 99%

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Chen

Park

Krishna

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multihop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8 mm within a single cycle, i.e. 8 hops with 1 mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.

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Application-Aware Topology Reconfiguration for On-Chip Networks

Cited by 94 publications

References 35 publications

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

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