Application analysis and resource mapping for heterogeneous network processor architectures

Ramaswamy, Ramaswamy; Weng, Ning; Wolf, Tilman

doi:10.1016/b978-012088476-6/50014-9

Cited by 14 publications

(17 citation statements)

References 21 publications

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“…Shah et al [8] present a technique for task allocation, also for network processors. Further work was presented by Ramaswami, et al [9], who used a randomized algorithm to assign task graphs to processing elements. However, none of the techniques presented in these works consider process transformation such as replication or merging which are essential (as we show later) for exploiting the full performance potential of SMP architectures.…”

Section: Problem Descriptionmentioning

confidence: 99%

Approximation Algorithm for Process Mapping on Network Processor Architectures

Ostler

Chatha

Konjevod

2007

2007 Asia and South Pacific Design Automation Conference

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Abstract-The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, and block multi-threading. The paper presents an automated system-level design technique for process mapping on such architectures with an objective of maximizing the worst case throughput of the application. As this mapping must be done in the presence of resource (processors and code size) constraints, this is an NP-complete problem [1]. We present a polynomial time approximation algorithm guaranteed to generate solutions with throughput at least 1 2 that of optimal solutions. The proposed algorithm was utilized to map realistic applications on the Intel IXP2400 (NP) architecture, and produced solutions within 78% of optimal.

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Section: Problem Descriptionmentioning

confidence: 99%

Approximation Algorithm for Process Mapping on Network Processor Architectures

Ostler

Chatha

Konjevod

2007

2007 Asia and South Pacific Design Automation Conference

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“…Ramaswamy et al [19] and Weng et al [20] presented randomization algorithms for task allocation on network processors with an objective of minimizing latency (not throughput) without considering multi-threading or process transformations. Ramamurthi et al [21] presented heuristic techniques for mapping applications to block multi-threaded multiprocessor architectures.…”

Section: Previous Workmentioning

confidence: 99%

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

Ostler

Chatha

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…To emulate pipelining, we employ a previously-proposed graph-clustering method that greedily clusters instructions with the highest control and data flow affinity [35] to 2 Except dh which is not packet based nor ssl because of its inlined console output.…”

Section: Udhcpmentioning

confidence: 99%

The case for hardware transactional memory in software packet processing

Labrecque

Steffan

2010

Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

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Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and accelerator cores per network node, it is a challenge to support sharing and synchronization across them in a way that is scalable and easy-to-program. In this paper, we focus on parallel/threaded applications that have irregular control-flow and frequently-updated shared state that must be synchronized across threads. However, conventional lock-based synchronization is both difficult to use and also often results in frequent conservative serialization of critical sections. Alternatively, we propose that Transactional memory (TM) is a good match to software packet processing: it both (i) can allow the system to optimistically exploit parallelism between the processing of packets whenever it is safe to do so, and (ii) is easy-to-use for a programmer. With the NetFPGA [1] platform and four network packet processing applications that are threaded and share memory, we evaluate hardware support for TM (HTM) using the reconfigurable FPGA fabric. Relative to NetThreads [2], our two-processor four-way-multithreaded system with conventional lock-based synchronization, we find that adding HTM achieves 6%, 54% and 57% increases in packet throughput for three of four packet processing applications studied, due to reduced conservative serialization.

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Application analysis and resource mapping for heterogeneous network processor architectures

Cited by 14 publications

References 21 publications

Approximation Algorithm for Process Mapping on Network Processor Architectures

Approximation Algorithm for Process Mapping on Network Processor Architectures

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

The case for hardware transactional memory in software packet processing

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