Approximation Algorithm for Process Mapping on Network Processor Architectures

Abstract

Abstract-The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, and block multi-threading. The paper presents an automated system-level design technique for process mapping on such architectures with an objective of maximizing the worst case throughput of the application. As this mapping must be done in the presence of resource (processors and code size) constraints, this is an NP-complete problem [1]. We present a polynomial time approximation algorithm guaranteed to generate solutions with throughput at least 1 2 that of optimal solutions. The proposed algorithm was utilized to map realistic applications on the Intel IXP2400 (NP) architecture, and produced solutions within 78% of optimal.

Approximation algorithm for data mapping on block multi-threaded network processor architectures

“…In this paper we focus on an automated technique for performing stage iii). Automated process mapping has been addressed elsewhere [6,7].…”

“…ILP formulations [5,6] and heuristic [6] approaches for application mapping on network processors have been proposed in the past. More recently Ostler et al [7] proposed an approximation algorithm for process mapping on network processors. In this paper we present an approximation algorithm for data mapping on block multi-threaded architectures.…”