Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT

Aouini, Sadok; Chuai, Kun; Roberts, G.W.

doi:10.1109/tcsi.2011.2161411

Cited by 14 publications

(12 citation statements)

References 14 publications

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“…The DUT for this simulation is modeled as an ideal 6th-order PLL with a bandwidth of 100 kHz [5]. The DUT is assumed noiseless.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…By selecting the appropriate loop-filter F(s), frequency-divider ration N PLL , the input-output phase transfer function Θ o /Θ i can be adjusted so that the desired frequency response is achieved. This principle was first used to generate test signals for evaluating the frequency response behavior of PLLs [17] and further expanded to high-order PLL design in [5].…”

Section: Continuous-time Phase Signal Generationmentioning

confidence: 99%

“…This process would be repeated over frequency so that a set of frequency-dependent calibration factors could be derived. A more detail description of this process is outlined in [5].…”

Section: System Calibrationmentioning

confidence: 99%

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A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Bielby

Chowdhury

et al. 2016

J Electron Test

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An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude-and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.cloud computing, etc. In order to keep component costs down, low-cost test techniques are essential. One strategy is to incorporate test circuits directly on-chip to standardize test equipment access, improve accuracy and repeatability, and to contribute to short test times through parallel test procedures. In some cases, an on-chip instrument may be the only means to capture information associated with some internal core circuit. An important attribute of such on-chip test circuits is a low silicon area overhead. In addition, such on-chip instruments are not bandwidth limited by the test channel, so tests can be performed at the desired operating frequencies and speeds [7]. A software programmable, probabilistic test instrument using ΣΔ-encoded phase/amplitude-signal generators is to be described in this paper.This work in a shorter form was first presented at the 20th International Mixed-Signal Testing Workshop [14]. In that publication the general concept of the probabilistic instrument was proposed and demonstrated with discrete components. In this publication, our first attempt at integrating the concept into a 130 nm CMOS IC realization. The results of this endeavor will also be described here. While our intent is to use this instrument as part of an embedded instrument for high-speed transceivers, however, at this point in time, the IC results do not operate anywhere close to the 1 Gbps rates required by today's I/Os. This is not meant to be a definitive statement that the approach is not sound but rather the results gather here is a testament of the working principle. It is expected that future work will improve the operating speed and measurement resolution suitable for next generation transceiver ICs. This paper will begin with a system overview of the probabilistic test instrument (PTI) in Section II, including a description of various methods for phase and voltage signal generation using sigma-delta encoding methods, and CDF extraction. Section III will describe the critical decision-making circuits such as the D-type flip-flops and comparator circuits used in the CMOS IC implementation. Section IV will describe the Responsible Editors:

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“…The DUT for this simulation is modeled as an ideal 6th-order PLL with a bandwidth of 100 kHz [5]. The DUT is assumed noiseless.…”

Section: Simulation Resultsmentioning

confidence: 99%

Section: Continuous-time Phase Signal Generationmentioning

confidence: 99%

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A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Bielby

Chowdhury

et al. 2016

J Electron Test

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“…From a system perspective, such a conversion process should always be combined with a reconstruction filter to eliminate the images in the output spectrum. In [2], it has been shown that a phase-locked loop can be used as a reconstruction filter for DTCs.…”

Section: Introductionmentioning

confidence: 99%

“…As the PLL in this implementation is used as a time domain filter, any PLL with the appropriate bandwidth may be used. PLLs have been demonstrated 2 Phase/frequency test signal generation process where a DC signal is encoded using sigma-delta modulation, converted to phase or frequency through a DTC or DFC, and reconstructed using a PLL serving as time/frequency domain filter to be built in 90 nm and 45 nm technologies; as such, the technique should be fully compatible with them. As this technique uses a bitstream and a PLL, it is scalable with technology and a higher speed implementation would be realizable.…”

Section: Introductionmentioning

confidence: 99%

High Speed On-Chip Signal Generation for Debug and Diagnosis

2012

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This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4 GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-fortest (DFT), or built-in self-test (BIST).

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CMOS time‐to‐digital converters for mixed‐mode signal processing

Yuan

2014

J. eng.

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Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT

Cited by 14 publications

References 14 publications

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

High Speed On-Chip Signal Generation for Debug and Diagnosis

CMOS time‐to‐digital converters for mixed‐mode signal processing

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