CMOS time‐to‐digital converters for mixed‐mode signal processing

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Mangia

Pareschi

et al. 2019

This paper presents the design of an ultra-low energy, rakeness-based compressed sensing (CS) system that utilizes time-mode (TM) signal processing (TMSP). To realize TM CS operation, the presented implementation makes use of monostable multivibrator based analog-to-time converters, fixedwidth pulse generators, basic digital gates and an asynchronous time-to-digital converter. The TM CS system was designed in a standard 0.18 µm IC process and operates from a supply voltage of 0.6V. The system is designed to accommodate data from 128 individual sensors and outputs 9-bit digital words with an average reconstruction SNR of 35.31 dB, a compression ratio of 3.2, with an energy dissipation per channel per measurement vector of 0.621 pJ at a rate of 2.23 k measurement vectors per second. Index Terms-compressed sensing, time-mode, time-mode signal processing, rakeness, energy efficiency, ultra-low energy

Section: B System Simulationsmentioning

confidence: 99%

“…Without transistors operating in the saturation region, it is very hard to realize signal processing and amplification functions in the analog domain. One possible solution to this problem is using time-mode signal processing (TMSP) techniques [1]- [4].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Multi-Sensor Compressed Sensing System Employing Time-Mode Signal Processing Techniques

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Mangia

Pareschi

et al. 2019

“…Without transistors operating in the saturation region, it is very hard to realize signal processing and amplification functions in the analogue domain. One solution to this problem is using time-mode signal processing (TMSP) techniques [17][18][19]. Time-mode (TM) circuits represent an analogue signal by the time difference between two binary switching events.…”

Section: Introductionmentioning

confidence: 99%

An energy efficient time-mode digit classification neural network implementation

Phil. Trans. R. Soc. A.

Mei

2019

This paper presents the design of an ultra-low energy neural network that uses time-mode signal processing). Handwritten digit classification using a single-layer artificial neural network (ANN) with a Softmin-based activation function is described as an implementation example. To realize time-mode operation, the presented design makes use of monostable multivibrator-based multiplying analogue-to-time converters, fixed-width pulse generators and basic digital gates. The time-mode digit classification ANN was designed in a standard CMOS 0.18 μm IC process and operates from a supply voltage of 0.6 V. The system operates on the MNIST database of handwritten digits with quantized neuron weights and has a classification accuracy of 88%, which is typical for single-layer ANNs, while dissipating 65.74 pJ per classification with a speed of 2.37 k classifications per second. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

“…This imposes a strict limit on the analog signal processing capabilities. One solution to this problem is using time-domain signal processing (TDSP) techniques [1]- [4]. A hypothetical timedomain/digital hybrid signal processing chain is shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

“…In addition to TDSP systems, TDCs find many applications in scientific experiments [5], such as digital phase-locked-loop (DPLL) applications [6], and on-chip time measurement and testing [7]. The simplest TDC implementation is based on a counter [1]. However, many TDCs employed today are based on simple delay lines and may be summarized as Flash TDCs [8], pipelined TDCs [9], [10], successive approximation TDCs [11]- [14], noise-shaping TDCs [15] and ∆ − Σ TDCs [5].…”

Section: Introductionmentioning

confidence: 99%

An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

2018

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a timedomain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm 2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.