AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface

Abstract

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations' performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication. The proposed architecture is fully scalable with the maximum matrix dimension limited by the available resources. In addition, a design environment is also developed, permitting assistance, through a friendly interface, from the customization of the hardware computing unit to the generation of the final synthesizable IP core. For N × N matrices, the architecture requires N ALU-RAM blocks and performs O(N 2 ), requiring N 2 + 7 and N + 7 clock cycles for matrix-matrix and matrix-vector operations, respectively. For the tested Virtex7 FPGA device, the computation for 500 × 500 matrices allows a maximum clock frequency of 346 MHz, achieving an overall performance of 173 GOPS. This architecture shows higher performance than other state-of-the-art matrix computing units.

A Scalable Architecture for Accelerating Multi-operation and Continuous Floating-point Matrix Computing on FPGAs

“…Another recent matrix computing structure based on circulant matrix have been proposed [27], which can handle multiple operations of matrix computing. But it only used for fixed-point data, which can not meet the needs of most engineering calculations.…”

“…In terms of integrating different functions of matrix operation in the same system, the two most relevant structures up to date have been designed by Wang et al [26] and Abbaszadeh et al [27].…”

“…Abbaszadeh et al [27] tried to design a matrix calculation unit based on the circulant matrix. This structure uses the DSP48E primitives embedded in FPGAs as a fixed-point multiply-accumulate functional unit, including a 48-bit pre-adder, a 23 × 28 multiplier, and a 48-bit multiplyaccumulate unit.…”

Real-Time Localization of Epileptogenic Foci EEG Signals: An FPGA-Based Implementation

“…This application needs a real-time implementation, and could be used as a help-decision tool by neurosurgeons to refine the localization of an epileptogenic area during resective epilepsy surgery. Note that the recent technology is mature enough to implement machine learning processes in real-time [27,28].…”

The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

“…FPGAs can also ensure highly accurate and short sampling periods, which are required for advanced motion control applications. A short processing time of control algorithms is also possible; however, the feature-rich FPGAs have overwhelming resources that are required for performing complex computation algorithms [17,18] yet are still expensive, which may prevent their further use in low-cost applications. One of the challenges in the electronics industry nowadays concerns fitting complex circuitry into small spaces.…”