Anomalous hot-carrier induced degradation in very narrow channel nMOSFETs with STI structure

Effects of Interface Trap Generation and Annihilation on the Data Retention Characteristics of Flash Memory Cells

“…However, there is a dimensional dependency of hot-carrier degradation properties of shallow-trench isolation (STI) transistors [7], [8], which showed that more interface traps are generated by STI edge stress for narrower width transistors after hotcarrier stress. However, their studies are limited to hot-carrier stress and the dimensions of transistors are larger than 100 nm.…”

Data retention characteristics of sub-100 nm NAND flash memory cells

“…From the extraction results in Fig. 2, we can notice that as the channel width decreases the interface trap generation by FN stress increases rapidly, which also can be explained by STI edge stress [4], [5]. As the interface trap generation increase rapidly for narrow width cells, it is a major degradation mechanism for sub-100 nm cells.…”

“…As the transistor sizes are scaled down, the oxide degradation characteristics of a large dimensional capacitor cannot be used for the prediction of a small dimensional transistor because there is a dimensional dependency of hot-carrier degradation properties [4], [5]. They showed that more interface traps are generated by STI edge stress for narrower width transistors after hot carrier stress.…”

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

“…Until now, the reliability comparison between the buried-and the surface-channel narrow-width p-MOSFETs fabricated by STI was reported [9]. Furthermore, the channelwidth dependences of the hot-carrier induced degradation have been studied for n-MOSFETs [6] and SOI n-MOSFETs [10], in which the narrow-width devices had inferior reliability due to the accelerated hot-carrier generation and the injection rates at the channel-region adjacent to the STI edge, and due to the lower gate-oxide-breakdown caused by the large edge current after the hot-carrier stressing around the channel-edge region, respectively. Consequently, twodimensional (2-D) analyses of the hot-carrier effects along the channel-width direction are necessary to realize high reliability CMOSFETs.…”

“…On the other hand, the isolation technology has shifted from the conventional LOCOS to the shallow trench isolation (STI) [3] as the technology nodes have been scaled down to submicron area, and the comparison of the device reliability dependent on the isolation technologies have been reported [4][5][6]. It is expected that the STI technology may modulate the high electric fields near the channelwidth edge resulting in the reliability variation along the channel-width direction, because the narrow-width or the inverse-narrow-width effects are largely influenced by the STI process [7,8].…”