Anomalous Behavior of Synchronizer and Arbiter Circuits

Chaney, T.J.; Molnar, Charles E.

doi:10.1109/t-c.1973.223730

Cited by 283 publications

(94 citation statements)

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“…In this state AB is true, and the output is 1. If we now set B to 0, we will move to state (1,0,1), and the output should remain 1. However, because of the delay in the inverter, the top AND gate will become false before the lower AND becomes true, and a 0 will propagate to the output.…”

Section: Fundamental Mode Huffman Circuitsmentioning

confidence: 99%

“…Referring to Figure 2, assume that we are in state (1, 1, 0), and we move to state (1, 0, 1) by changing both B and C. If the delays in the circuit are slightly greater for input C, the circuit will momentarily be in state (1, 0, 0), and the output will go to 0 (a dynamic hazard). We could try to alter the circuit delays to make sure that the circuit goes through state (1,1,1) instead, but what if this state had also been set to 0 in the original Karnaugh map? In this case, no intermediate state will maintain the correct output, and an unavoidable hazard is present.…”

Section: Fundamental Mode Huffman Circuitsmentioning

confidence: 99%

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Asynchronous design methodologies: an overview

1995

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Asynchronous design has been an active area of research since at least the mid 1950's, but has yet to achieve widespread use. We examine the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies. These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and compilation-based quasidelay-insensitive circuits.

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Section: Fundamental Mode Huffman Circuitsmentioning

confidence: 99%

Section: Fundamental Mode Huffman Circuitsmentioning

confidence: 99%

Asynchronous design methodologies: an overview

1995

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“…Many researchers have directly observed metastability in bistable logic devices with both ordinary and sampling oscilloscopes [1,2,5]. Others have adduced statistical proof of the existence of metastability [3,4].…”

Section: Ii_mentioning

confidence: 99%

A solution to a special case of the synchronization problem

Stewart

Ward

1988

IEEE Trans. Comput.

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Perfectly synchronizing an asynchronous digital signal in bounded time is known to be impossible, since all bistable devices exhibit a region of metastability. In practice, "reliable synchronization" means the achievement of a synchronization failure rate comparable to hardware failure rates. Since metastable state decay times are exponentially distributed, an arbitrarily low synchronization failure rate can be achieved by performing the synchronization with a shift register of

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“…Unfortunately, there is no upper bound for the time the flip-flop may stay in the metastable state. This phenomenon is known as the metastability phenomenon [3,13]. It is sometimes referred to as the glitch phenomenon.…”

Section: Introductionmentioning

confidence: 99%

The Nature of Delay-Insensitive Computing

Rem

1991

Workshops in Computing

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Citation for published version (APA): Rem, M. (1990). The nature of delay-insensitive computing. (Computing science notes; Vol. 9020). Eindhoven: Technische Universiteit Eindhoven. Document status and date:Published: 01/01/1990 Document Version:Publisher's PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication:• A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal.If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policyIf you believe that this document breaches copyright please contact us at:openaccess@tue.nl providing details and we will investigate your claim. Delay-insensitive systems are systems whose correct functioning does not depend on delay assumptions. In this paper a gradual introduction to delayinsensitivity is given, illustrated by many examples. Precise definitions are given of delay-insensitivity, decomposition (or refinement), and speed-independence. Recent results of the associated theory are touched upon.

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Anomalous Behavior of Synchronizer and Arbiter Circuits

Cited by 283 publications

References 1 publication

Asynchronous design methodologies: an overview

Asynchronous design methodologies: an overview

A solution to a special case of the synchronization problem

The Nature of Delay-Insensitive Computing

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