Annealing properties of ion-implanted <i>p-n</i> junctions in silicon

Michel, A. E.; Fang, F. F.; Pan, Er

doi:10.1063/1.1663714

Cited by 56 publications

(18 citation statements)

References 7 publications

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“…5 and 6, the magnitude of leakage current appears low (20) and similar in both processes, although LOCOS results indicate better process control because of the gaussian shape of the histogram and smaller standard deviation. 5 and 6, the magnitude of leakage current appears low (20) and similar in both processes, although LOCOS results indicate better process control because of the gaussian shape of the histogram and smaller standard deviation.…”

Section: Resultsmentioning

confidence: 89%

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Ghezzo

Kaminsky

Nissan-Cohen

et al. 1989

J. Electrochem. Soc.

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Local oxidation of polysilicon over silicon (tOPOS) isolation has been characterized for use in a 0.8 ~m CMOS/BULK process with reduced field oxide edge encroachment (bird's beak). Compared to the standard local oxidation of silicon (LOCOS) LOPOS adds a thin polysilicon layer between the stress relief oxide and the overlying nitride without changing the active area patterning procedure. To optimize the LOPOS structure, the thickness of the oxide and nitride layers was varied in a fully-factorial experiment, measuring the bird's beak and checking for the presence of silicon edge defects. It was found }hat for a 6000A field oxide the bird's beak can be safely reduced to =0.3 I~m per side with tOPOS, which is significantly less than =0.55 ~m with LOCOS. The corresponding stack consisted of 1500,~ Si3N4/550A polysilicon (undoped)/ 200A SiO2. LOPOS fabricated diodes exhibited low leakage of <0.5 nA/cm 2 and <0.5 pA/cm for the area and edge components, respectively, while MOS capacitors were breakdown-free up to 8 MV/cm during voltage-stress tests, compared to 6 MV/cm for LOCOS. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 157.182.150.22 Downloaded on 2015-04-12 to IP

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Section: Resultsmentioning

confidence: 89%

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Ghezzo

Kaminsky

Nissan-Cohen

et al. 1989

J. Electrochem. Soc.

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“…12,13 These contaminants act as nucleation sites for dislocation loop formation during SPE in the postimplantation annealing. By eliminating such contamination sources as completely as possible, junctions having leakage currents about four orders of magnitude smaller than previously reported data 4,5 have been obtained at an annealing temperature as low as 450°C. 13 However, this leakage current is still about two orders of magnitude higher than that obtained with high-temperature ͑1000°C͒ annealing.…”

Section: Introductionmentioning

confidence: 80%

“…[5][6][7] This is due to the residual damage existing beyond the location of amorphous/crystalline ͑A/C͒ interface, [8][9][10] which is known as so-called end-of-range ͑EOR͒ defects. ͑It is classified as category II defects in Ref.…”

Section: Introductionmentioning

confidence: 99%

Influence of substrate-boron concentration on the residual end-of-range defects in 450 °C annealed As+-implanted junctions

Nakada

Oka

Tamai

et al. 1996

Journal of Applied Physics

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Evolution of the crystallographic position of As impurities in heavily doped Si crystals as their electrical activity changes Appl.In order to clarify the origin of enhanced leakage currents observed in As ϩ -implanted junctions annealed at a temperature as low as 450°C ͓M. M. Oka, A. Nakada, K. Tomita, T. Shibata, T. Ohmi, and T. Nitta, Jpn. J. Appl. Phys. 34, 796 ͑1995͔͒, two-step implantation/anneal experiments have been conducted and the spatial distribution of end-of-range defects has been investigated. As a result, it has been demonstrated that the residual damage in 450°C annealed junctions is strongly influenced by the doping level of p-type silicon substrate. The defects were found deeply distributing in the substrate, i.e., about 350 nm below the silicon surface when the doping level was 2.5ϫ10 15 cm Ϫ3 . The defect distribution further extends for higher boron doping levels. Taking these experimental results into account, As ϩ -implanted n ϩ p junctions were formed on substrates having varying doping levels. About two orders of magnitude reduction in the leakage current was observed with decrease in the substrate boron concentration from 10 16 to 10 14 cm Ϫ3 . For low boron concentration of 1.6ϫ10 14 cm Ϫ3 , the leakage current level as low as 1.7ϫ10 Ϫ9 A/cm 2 has been achieved by a 450°C postimplantation annealing.

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“…Molecular beam epitaxy (MBE) and other thin film growth techniques are increasingly used to form epitaxial silicon-based device structures employing Ge and/or SiGe alloy layers (1). In the fabrication of these structures it is often required to make contact to a buried SiGe or Si layer.…”

Section: Selective Dry Etching Of Germanium With Respect To Silicon Andmentioning

confidence: 99%

“…It is known that the leakage current is increased and device properties are degraded in the p-n junction regions traversed by the dislocations (1). It is known that the leakage current is increased and device properties are degraded in the p-n junction regions traversed by the dislocations (1).…”

mentioning

confidence: 99%

A Mechanism of the Sidewall Process Induced Junction Leakage Current of LDD Structure

Onishi¹,

Ayukawa²,

Tanaka³

et al. 1991

J. Electrochem. Soc.

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In MOSFETs with lightly doped drain (LDD) sidewall spacers, drain-to-substrate leakage is caused by the crystalline defects at the sidewall edge. To clarify the mechanism of the defect generation, the recrystallization process after highconcentration As + implantation was observed by means of cross-sectional TEM with in situ annealing. During the heating process, solid phase epitaxial regrowth did not proceed in the lateral direction at the Si surface of the sidewall edge and the defects were pinning there. However, during a subsequent quick cooling period, the crystalline defects grew to a high degree in the (111) direction at the sidewall edge. When the recrystallization was performed without the sidewall, the defects are not generated. From these results, it was determined that the stress from the sidewall contributes greatly to the defects growth. The crystalline defects at the sidewall edge can be suppressed by fabricating a smoothly shaped sidewall that decreases stress, so that stable draln-to-substrate properties can be obtained.

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Annealing properties of ion-implanted p-n junctions in silicon

Cited by 56 publications

References 7 publications

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Influence of substrate-boron concentration on the residual end-of-range defects in 450 °C annealed As+-implanted junctions

A Mechanism of the Sidewall Process Induced Junction Leakage Current of LDD Structure

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