Annealing of heavy-ion induced floating gate errors: LET and feature size dependence

Abstract

We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of rough bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes

Alpha-induced soft errors in Floating Gate flash memories

“…In fact, a higher V th means a higher electric field in the tunnel oxide, hence higher charge loss for a given ion strike [9], [10]. This is in agreement with our experimental results for 50-nm devices, which show that the cross section increases going from L0 to L3 (see Fig.…”

“…4. This is in agreement with the behavior reported after heavy-ion exposure [10] and also after TID irradiation [11]. For converse, the increase of intrinsic errors as time passes is negligible in a fresh, non-irradiated device, in the considered timeframe (Fig.…”

Increase in the Heavy-Ion Upset Cross Section of Floating Gate Cells Previously Exposed to TID

“…It is worth to note that all the post-radiation measurements throughout this work (after both TID and heavy-ion exposure) were performed several days after exposure, when most of the post-radiation annealing of FG errors was practically over (the tunnel oxide is only 10-nm thick in these devices). As a consequence, annealing phenomena [13], [14] are accounted for and the errors we detect in the cells can be mainly attributed to charge loss from the Floating Gate [11]. We recall that all the peripheral circuitry was shielded during all irradiations, so that any effect in the control building blocks can be ruled out.…”

“…This procedure was repeated on 10 FG memory sectors (each made of cells) to gain enough statistical accuracy (in the order of thousands of errors per experimental point). All the measurements have been performed several days after both TID and heavy-ion exposure, when the bulk of post-radiation annealing phenomena [13], [14] can be considered over.…”

Effects of Total Ionizing Dose on the Retention of 41-nm NAND Flash Cells

“…HT retention test, up to 1000 hrs, at 150 C, after reprogramming the irradiated cells. Retention tests (both room-temperature and high-temperature) on the irradiated devices were carried out a few days after TID exposure (due to the technical time to ship the wafers to the manufacturer, which performed the retention tests with special wafer-level equipment), when the bulk of annealing phenomena are practically over [9], [10]. All the wafers have been kept in the same conditions to make comparisons meaningful.…”