AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing

Abstract

In this work, we propose a multi-bit precision (4b input, 4b weight and 4b output) in-memory computing (IMC) architecture, based on the voltage scaling and charge sharing scheme, for the artificial intelligence (AI) edge devices. To achieve the efficient computation, a new AND logic based 8T SRAM cell (AND8T) has been used which employs the charge-domain based computation. For such computation, AND8T incorporates an overlaying metal-oxide-metal capacitor (MOM cap) with no bitcell area overhead. The proposed cell mitigates the linearity issue of multiply and accumulate (MAC) operation for the IMC unit which is highly desirable for the reliable operation of complex neural networks (CNN). Moreover, our high precision AND8T based IMC architecture allows 128 parallel MAC operations avoiding the need of serial multi-bits input implementation through multiple cycles. The proposed design has been successfully verified by the monte carlo simulation results while working at 50MHz clock frequency and 1V supply using standard 65nm node.

Memristive Devices for Time Domain Compute-in-Memory

“…By employing wave pipelining as shown in [9] computations can be overlapped, speeding up the time per computation in a chain from t min + ∆t to ∆t. By considering 1 Area∆t as a figure of merit for the throughput, the presented design also proves advantageous. Multi-bit TDCIM is mostly implemented in a bit-serial fashion.…”

“…To tackle both of these challenges, new schemes for computation have emerged, that take inspiration from the human brain, i.e., the domain of neuromorphic computing. Thereby, one key principle is to compute-in-memory (CIM), an approach that co-locates data and computation to address the von-Neumann bottleneck [1].…”

“…The resilience of deep neural networks to a certain degree of imprecision is exploited with a moderate impact on the classification accuracy [2]. While current and charge domain computing have enjoyed high popularity for CIM [1], [3], [4], [5], they require expensive analog-to-digital conversion and lack in ability of voltage scaling. A different compute scheme is time domain computein-memory (TDCIM).…”

“…The total time is given by Eq. (1), with N as the number of multiply and accumulate (MAC) operations and I MAC as the current component of a single MAC operation.…”

An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

“…Here, each storage element implements single-bit multiplication, which is a part of a larger operation [5]. By employing different types of arithmetic units in memory cells, various types of IMC architectures were developed in [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]. These works aim to improve energy consumption, speed, and accuracy.…”