Analyzing the Impact of NBTI and Process Variability on Dynamic SRAM Metrics Under Temperature Variations

Picardo, Siona Menezes; Shaik, Jani Babu; Sahni, Sakshi; Goel, Nilesh; Singhal, Sonal

doi:10.1007/978-981-15-4775-1_66

Cited by 2 publications

(1 citation statement)

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“…Device and circuit reliability analysis has been an integral part of the design process. It enables the identification and evaluation of probable faults from degradation issues 20,21,24–26 . Fault rectification in circuits can also be mitigated through “reliability‐aware designs.” It aims at solving degradation factors to ensure resilient system designs 27–31 .…”

Section: Introductionmentioning

confidence: 99%

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

Picardo

Shaik

Singhal

et al. 2022

Circuit Theory & Apps

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Reliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS-based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation.However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential "integrate and fire" (I&F) model-based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability-aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at "Time0" (pre-degradation) and "Aged" (post-degradation) neuron netlists, which is then compared with the proposed reliability-aware circuit.

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Section: Introductionmentioning

confidence: 99%