Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

Kim, Nam Sung; Draper, Stark C.; Zhou, Shi-Ting; Katariya, Sumeet; Ghasemi, Hamid; Park, Taejoon

doi:10.1109/tvlsi.2011.2173220

Cited by 12 publications

(4 citation statements)

References 11 publications

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“…For accurate characteristics, we use 32-nm PTM High k/Metal-gate technology [26] (low-V th0 nMOS = |low-V th0 pMOS | = 0.49 V; high-V th0 nMOS = |high-V th0 pMOS | = 0.65 V; V DD = 0.9 V) and perform HSPICE simulations in the following analysis. To capture the process variation, the threshold voltage (V th ) variation for an nMOS (pMOS) transistor with minimum size is 24 mV (29.2 mV) [27]. Fig.…”

Section: Tm-rf: Circuit Implementationmentioning

confidence: 99%

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

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Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.Index Terms-Leakage current, low power, bias temperature instability (NBTI/PBTI), process variation, register file (RF). 1063-8210

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Section: Tm-rf: Circuit Implementationmentioning

confidence: 99%

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

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“…As this has become more challenging, several authors have proposed methods to improve SRAM reliability in the presence of NBTI/PBTI and GOBD degradation. These approaches include circuitry that periodically flips the data in an SRAM cell to reduce failure rates [66], the use of redundancy [67]- [69], error correcting codes [70], [71], and both [72]. Evaluation of these methods requires a model of cell stress.…”

Section: Chapter 2 Backgroundmentioning

confidence: 99%

System-level modeling and reliability analysis of microprocessor systems

Chen

Milor

2013

5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI

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I am particularly thankful to my parents, Lo-Wen Chen and Shu-Yuan Tang, who have always been on my side, for their love and encouragement throughout my life. I also thank my grandfather, grandmothers, brother, Hsuan-Chih Chen, and sister, Jou-Chou Chen, for their love and support. Last but not least, I would like to thank all the professors, teachers, families, and friends who guided me to become the person that I am today.v

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“…However, those cheap devices, especially SRAM parts in the embedded systems, are vulnerable to the radiation effects. Due to the feedback mechanism for data retention in the SRAMs, the bit flips occur frequently in the high radiation environments [16]. The SRAM parts have to be hardened for radiation tasks.…”

Section: Introductionmentioning

confidence: 99%

A self-scrubbing scheme for embedded systems in radiation environments

Zhai

Saha

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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SRAMs are very sensitive to radiation effects. When embedded systems working in the extreme radiation environments, bit flips may occur frequently and decrease the reliability of the systems significantly. In this paper, a self-scrubbing scheme is proposed for embedded systems in extreme radiation environments. In the proposed scheme, both scrubbing and error correcting codes are used to mitigate a large number of the errors in the RAMs. Along with this, a separate scrubber is designed to scrub the RAM independently, when the CPUs are busy. In addition, the scrubber is a portable module and the hardware cost does not grow with the size of the available RAM. The results of the experiments show that, in the neutron radiation environments where the error rate in the unhardened RAMs is approximately 1.2bit/(KB•h), while the error rate of the self-scrubbing RAMs is less than 8.7 × 10 −5 bit/(KB•h), which is one fifth of the error rate of the conventional ECC RAMs.

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Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

Cited by 12 publications

References 11 publications

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

System-level modeling and reliability analysis of microprocessor systems

A self-scrubbing scheme for embedded systems in radiation environments

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