Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction

Lee, Keun-Ho; Park, Jin‐Kyu; Yoon, Young-Nam; Jung, Dai-Hyun; Shin, Jai-Pil; Park, Young-Kwan; Kong, Jeong-Taek

doi:10.1109/iedm.2001.979600

Cited by 13 publications

(1 citation statement)

References 3 publications

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“…Moreover, dealing with the coupling capacitance due to metal filling is a complex problem, especially because several ways of filling can be found in the industry. While [6] demonstrates metal filling impact on circuit performing a full-chip RC extraction, reference [7] studies the capacitance deviation due to both dummy fills and modifications of interconnect geometry. Filling guidelines for one metal layer are exposed in [8] in order both to increase metal density and to reduce dummy fills impact.…”

Section: Introductionmentioning

confidence: 99%

Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept

Remy¹,

Coll²,

Picot³

et al. 2020

JICS

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The objective of this paper is to evaluate the delay impact of staggered metal filling on the standard cells and their associated local interconnect on several metal levels. A Design of Experiment (DOE) is used to define a large range of filling pattern shapes and positions. This set of filling patterns is then inserted in a Ring Oscillator (RO). From the filled RO simulations, the RO delay is expressed as a function of the filling pattern features. The maximal timing error between the model and the simulation is 1.3%, validating the model. The filling impact on RO delay magnifies the one introduced by the front-end process variations (PVT). Consequently, the filling influence is introduced for the minimal, typical and maximal corners, defined now with Process (P), Voltage (V), Temperature (T) and Filling density (F) characteristics.

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Section: Introductionmentioning

confidence: 99%

Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept

Remy¹,

Coll²,

Picot³

et al. 2020

JICS

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Impact of substrate resistivity on spiral inductors at mm-wave frequencies

Nyssens

Rack

Schwan

et al. 2022

Solid-State Electronics

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Test structure generation to quantify filling impact

Remy

Portal

Coll

et al. 2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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In present and future technology nodes, the insertion of metal filling can lead to timing yield losses. In this paper, we present a test structure generation method to study the impact of metal filling on interconnect timings. Such a method is mandatory when dealing with metal filling, because its insertion in real design does not follow standardized rules. The proposed test structure generation method is based on Design Of Experiment (DOE) to minimize the number of structures. The DOE approach links test structures timings to filling pattern characteristics. This timing model is first validated by comparison with the test structures electrical simulations. Then the model is used for statistical analysis about filling impact depending on metal level.

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Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction

Cited by 13 publications

References 3 publications

Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept

Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept

Impact of substrate resistivity on spiral inductors at mm-wave frequencies

Test structure generation to quantify filling impact

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