Proceedings of IEEE VLSI Test Symposium
DOI: 10.1109/vtest.1994.292288
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Analyzing the design-for-test techniques in a multiple substrate MCM

Abstract: This paper discusses the results of several Design-For-Testability techniques implemented in a Multichip Module (MCM). MCM test issues discussed includeboundary scan, Built-In-Self-Test (BIST), concurrent test sequencing, and module level test.Analyzing the results of the D m attributes is necessary to determine effectiveness of the overall test strategy, improve upon various techniques, and leam lessons that may be carried into subsequent generations of MCM design. A discussion of the analysis and the lessons… Show more

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Cited by 10 publications
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“…6 GHz. Even though these speeds are attainable, the equipment cost is very high (-$10k per channel).…”
Section: Introductionmentioning
confidence: 99%
“…6 GHz. Even though these speeds are attainable, the equipment cost is very high (-$10k per channel).…”
Section: Introductionmentioning
confidence: 99%
“…Like most test problems, they boil down to controllability and observability problems -combining several VLSI components in a small package limits test accessibility. This causes problems for test generation and the application of test vectors using test equipment [2,3,4]. One method to lessen the burden on these test steps is to increase the controllability and observability.…”
Section: Introductionmentioning
confidence: 99%