Analyzing Parallel Programs with Pin

Bach, Moshe; Charney, Mark; Cohn, Robert; Demikhovsky, Elena; Devor, Tevi; Hazelwood, Kim; Jaleel, Aamer; Luk, Chi-Keung; Lyons, Gail; Patil, Harish; Tal, Ady

doi:10.1109/mc.2010.60

Cited by 89 publications

(44 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since SAMMU is an extension to the current MMU hardware, we simulate its behavior with the Pin [2] dynamic binary instrumentation tool. The simulated hardware uses the same TLB configuration as the real machines.…”

Section: Methodsmentioning

confidence: 99%

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Cruz

Diener

Pilla

et al. 2016

Euro-Par 2016: Parallel Processing

View full text Add to dashboard Cite

Abstract. In modern shared-memory architectures, it is important to map threads and data in a way that increases the locality of their memory accesses, thereby improving performance and energy efficiency. Threads that access shared data should be mapped close to each other in the memory hierarchy, while the data they access should be mapped to their NUMA node, which is called sharing-aware mapping. In this paper, we propose SAMMU, which adds sharing-awareness to the memory management unit in current architectures. SAMMU analyzes the memory access behavior in hardware and provides information to the operating system so it can perform an online mapping of threads and data. In the evaluation with a wide range of parallel applications, performance was improved by up to 35.7% (13.1% on average).

show abstract

Section: Methodsmentioning

confidence: 99%

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Cruz

Diener

Pilla

et al. 2016

Euro-Par 2016: Parallel Processing

View full text Add to dashboard Cite

show abstract

“…Thus, it is hard to be implemented because of the difficulty of the code rewriting at run-time. Nonetheless, dynamic analysis for complex programs can be built with the dynamic binary instrumentation frameworks, such as DynamoRIO [21], Valgrind [212], and Pin [23][24].…”

Section: Happens-before Analysismentioning

confidence: 99%

Effective Monitoring Memory Operations for Dynamic Race Detection through Hierarchical Filtering Method

Ha¹,

Jun²

2014

IJMUE

View full text Add to dashboard Cite

show abstract

“…Hornet [19] is a cycle accurate NoC simulator that can be driven by traces, by a built-in MIPS simulator or by native applications instrumented by Pin [5]. Garnet [2] also provides a cycle accurate model, and can interface with Gems to model a full system, and with ORION [39] to provide power estimates.…”

Section: Simulation Of Future Many-core Systemmentioning

confidence: 99%

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Navaridas

Khan

et al. 2012

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

View full text Add to dashboard Cite

Abstract-Architectural simulation is an essential tool when it comes to evaluating the design of future many-core chips. However, reproducing all the components of such complex systems precisely would require unreasonable amounts of computing power. Hence, a trade off between accuracy and compute time is needed. For this reason most state-of-the-art tools do not have accurate models for the networks-on-chip, and rely on timing models that permit fast-simulation. Generally, these models are very simplistic and disregard contention for the use of network resources. As the number of nodes in the network-on-chip grows, fluctuations with contention and other parameters can considerably affect the accuracy of such models. In this paper we present and evaluate a collection of timing models based on a reservation scheme which consider the contention for the use of network resources. These models provide results quickly while being more accurate than simple no-contention approaches.

show abstract

Analyzing Parallel Programs with Pin

Cited by 89 publications

References 7 publications

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Effective Monitoring Memory Operations for Dynamic Race Detection through Hierarchical Filtering Method

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Contact Info

Product

Resources

About