Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Roy, Nirmal; Gupta, Abhinav; Rai, Sanjeev

doi:10.1016/j.mejo.2015.07.009

Cited by 45 publications

(7 citation statements)

References 32 publications

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“…It is evident from Fig. 1 that the general construction is of GAA type [11] and the reasons for this design along with its merits are discussed at length in this section. The stability, power consumption, and I ON /I OFF current of any semiconductor device depend on the measure of gate controllability achievable for them.…”

Section: Device Dimensionsmentioning

confidence: 99%

Design and investigation of doping-less gate-all-around TFET with Mg₂Si source material for low power and enhanced performance applications

et al. 2023

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The MOSFET faces the major problem of being unable to achieve a subthreshold swing (SS) below 60 mV/dec. As device dimensions continue to reduce and the demand for high switching ratios for low power consumption increases, the TFETs (Tunnel Field Effect Transistors) appears to be a viable device, displaying promising characteristic as an answer to the shortcomings of the traditional MOSFETs. So far, TFET designing has been a task of sacrificing higher ON state currents for low subthreshold swing (and vice versa), and a device that displays both while maintaining structural integrity and operational stability lies in the nascent stages of popular research. This work presents a comprehensive analysis of a heterojunction plasma doped gate-all-around TFET (HPD-GAA-TFET) with a comparison between Mg2Si and Si as source material. Charge plasma technique has been employed to induce doping in an intrinsic silicon wafer with the help of suitable electrodes. A low-energy bandgap material, i.e., Magnesium Silicide has been incorporated as source material to form a heterojunction between source and silicon-based channel. A rigorous performance comparison between Si-based GAA-TFET and HPD-GAA-TFET has been drawn with respect to electrical, RF, linearity, and distortion parameters. It is observable that HPD-GAA-TFET outperforms conventional Si-based GAA-TFET presenting an ON-state current (ION), SS, threshold voltage (Vth), and current switching ratio as 0.377 mA, 12.660 mV/dec, 0.214 V, and 2.985×1012,respectively. Moreover, HPD-GAA-TFET holds faster switching in contrast to Si-based device and is also more reliable. Therefore, HPD-GAA-TFET shows suitable candidature for low-power applications.

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Section: Device Dimensionsmentioning

confidence: 99%

Design and investigation of doping-less gate-all-around TFET with Mg₂Si source material for low power and enhanced performance applications

et al. 2023

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“…In-order to simulate the low power analog and digital circuits using proposed JL-DG MOSFET, eld-dependent saturation model, concentration-dependent mobility model, constant-voltage-temperature (CVT) model, Lombardi mobility model, and Shockley-Read-Hall recombination model have been used. [11][12].…”

Section: Device Structurementioning

confidence: 99%

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

Gupta¹,

Kumar

Pandey³

et al. 2021

Silicon

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The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nanometer regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Ampli ers and inverters are the basic building block of electronic ICs. A MOS ampli er converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage ampli er and differential ampli er have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device's response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm technology node have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

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“…7. It can be observe that cut-off frequency increases rapidly after gate voltage equal to threshold voltage of respective devices, and although JLTG shows higher cut-off frequency for the whole range of gate voltage, JL-GAA shows a significantly high peak in GTFP, indicating a better trade-off point [22]. Also, higher cut-off frequency in JLTG device signals lower delay time for electrons to transit from source to drain [23,24].…”

Section: Rf Performancementioning

confidence: 99%

A Comparative Investigation of SiGe Junctionless Triple Gate (JLTG) and Junctionless Gate-All-Around (JL-GAA) MOSFET

Gupta¹,

Varshney²,

Vishwakarma³

et al. 2021

Lecture Notes in Electrical Engineering

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According to the International Technology Roadmap for Semiconductors (ITRS) roadmap [1], the MOSFET sizes shrinking conventionally down to the nanometer regime. We are facing with short channel effects (SCEs) [2, 3] like poor sub-threshold swing, high drain-induced-barrier-lowering (DIBL), increased leakage currents, etc., leading to sub-optimal performance of transistors [4,5]. Researchers have studied several architectures and techniques like junctionless devices [6], multi-gate architecture [7], hetero-high-κ gate oxides [8], lower doping concentrations, high mobility substrate materials that allow lower device size, but without the disadvantage of severe SCEs [9, 10]. Saini et al. showed that among all other multi-gate architectures, triple gate junctionless devices exhibit superior gate controllability [11-14].Recently, gate-all-around nanowire has become a promising architecture for scaling of MOSFETs [15,16].In this paper, we compare two junctionless multi-gate (JLMG) architectures: junctionless gate-all-around (JL-GAA) and junctionless triple gate (JLTG) each with different high-κ gate oxides to further improve the gate control. These devices derive the advantage of high mobility of Silicon-Germanium material (1538 cm 2 /V • s at 6 × 10 17 cm −3 doping) [17]. Section 2 explains the structure and simulation of these devices. Section 3 comprises extensive comparison between the devices basis electrostatic, analog and RF parameters. Conclusions are summarized in Sect. 4.

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Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Cited by 45 publications

References 32 publications

Design and investigation of doping-less gate-all-around TFET with Mg₂Si source material for low power and enhanced performance applications

Design and investigation of doping-less gate-all-around TFET with Mg₂Si source material for low power and enhanced performance applications

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

A Comparative Investigation of SiGe Junctionless Triple Gate (JLTG) and Junctionless Gate-All-Around (JL-GAA) MOSFET

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Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Cited by 45 publications

References 32 publications

Design and investigation of doping-less gate-all-around TFET with Mg2Si source material for low power and enhanced performance applications

Design and investigation of doping-less gate-all-around TFET with Mg2Si source material for low power and enhanced performance applications

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

A Comparative Investigation of SiGe Junctionless Triple Gate (JLTG) and Junctionless Gate-All-Around (JL-GAA) MOSFET

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Design and investigation of doping-less gate-all-around TFET with Mg₂Si source material for low power and enhanced performance applications

Design and investigation of doping-less gate-all-around TFET with Mg₂Si source material for low power and enhanced performance applications