Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs

Ultralow-Power Device Operation

“…A prominent advantage of fully depleted SOI MOSFETs formed on good-quality thin film is due to the possible improvement of the subthreshold swing as compared to partially depleted Si film or bulk silicon transistors. The equivalent circuits in weak inversion of a bulk-like MOSFET (bulk or partially depleted SOI transistor) and a fully depleted SOI MOSFET [12,13] and/or a low doping density in the silicon substrate (under the buried oxide) leading to small buried oxide and substrate (depletion) capacitances, the subthreshold swing S can be substantially lower than that observed in bulk devices. For small interface state densities at the various Si/SiO 2 interfaces, which is usually the case for present technologies, the swing can reach the minimum theoretical limit of about 60 mV/dec at 300 K [10][11][12][13][14].…”

“…The facts that the current drive of the VI-MOSFET is governed by two, three, or four gates and that carriers are no longer confined at one interface present remarkable advantages: enhancement of the number of minority carriers, increase in carrier mobility and velocity due to reduced influence of scattering associated with oxide charges and surface roughness, increase in drain current and transconductance, reduced short-channel effects, and ideal subthreshold slope [22,23]. The subthreshold slope S vi and threshold voltage V t of the VI-MOSFET are calculated using a constant potential in the whole silicon layer [13,24], which is a very good approximation for V g V t :…”

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

“…In the case of VFD SONFET, two-dimensional analysis is necessary for any length of the gate. The existing compact models for fully-depleted SOI [13] and SON [14] structures have the bulk-Si substrate as the back-gate and, therefore, do not capture the operation of the VFD SONFET without the substrate. The two-dimensional coupling from the back side of the channel is similar to the lateral recessed source/drain ultra-thin body (UTB) SOI MOSFETs (Fig.…”

Threshold voltage modeling and performance comparison of a novel linearly graded binary metal alloy gate junctionless double gate metal oxide semiconductor field effect transistor

“…However, following the current trend of continuous device miniaturization, performance of conventional bulk silicon devices is facing severe limitations such as impurity induced carrier mobility degradation, an increased gate tunneling effect caused by a reduction in gate oxide thickness and a significant increase in p-n junction leakage current due to shallower junctions [1][2][3]. In order to alleviate the shortcomings of conventional bulk devices, several non-conventional multiple gate device structures have been proposed, out of which, double gate metal oxide semiconductor (DG MOS) structures have attracted significant research attention due to their superior scalability, excellent short channel effect reducing capability, ideal sub-threshold swing, double on current and excellent gate control over the channel, thereby pushing device dimension beyond the scaling limits posed by conventional fabrication technologies [4][5][6].…”