Analytical models for the electric field distributions and breakdown voltage of Triple RESURF SOI LDMOS

Hu, Xin; Zhang, Bo; Luo, Xiaorong; Li, Zhaoji

doi:10.1016/j.sse.2011.12.010

Cited by 26 publications

(11 citation statements)

References 8 publications

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“…To further deplete the drift region and obtain a better FoM, additional layers are created. Double-RESURF and triple-RESURF are extensively studied, 5,6 and recently, a quadruple-RESURF design is proposed. 7 The latter involves the middle-end of line (MEOL).…”

Section: Introductionmentioning

confidence: 99%

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Houadef

Djezzar

2021

Int J RF Microw Comput Aided Eng

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In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (R ON,SP ) is 94 mΩmm 2 , and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (g m ) at high gate voltages, with acceptable off-state leakage current (I off ), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (f MAX ) and cutoff frequency (f T ) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

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Section: Introductionmentioning

confidence: 99%

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Houadef

Djezzar

2021

Int J RF Microw Comput Aided Eng

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“…Due to the electrical isolation by BOX, SOI RESURF has the advantages of low leakage current, higher switching speed, considerable reduction in parasitic capacitance, and so on compared with the bulk silicon RESURF device. [6][7][8][9][10][11][12][13][14] Meanwhile, the breakdown mechanism of SOI RESURF is different from that of bulk silicon RESURF. [13][14][15][16] The study on the breakdown model is helpful to ascertaining the breakdown mechanism and providing guidance on structural optimization design.…”

Section: Introductionmentioning

confidence: 99%

“…[5,9,10] Although 2D models can effectively analyze the 2D electric field and potential distribution, mathematical expressions are very complicated and lacking in clear physical meaning. [7][8][9][10][11][12] In this paper, we present a simple 1D analytical RESURF model of the SOI lateral power device based on charge sharing and lateral graded approximation. It is suggested that a lateral junction with linearly effective doping concentration should consider the 2D coupling effect and give a novel explanation for the lateral field reshaping/reduction effects.…”

Section: Introductionmentioning

confidence: 99%

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

Zhang

Guo

et al. 2015

Chinese Phys. B

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A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.

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“…Therefore, the main issue concerning the design of LDMOS is the trade-off between breakdown voltage and specific on-resistance. [2] In the past years, Reduce Surface Field(RESURF) technologies, including single-RESURF, double-RESURF, and triple-RESURF [3][4][5] were introduced into LDMOS to obtain a suitable trade-off between BV and R sp . But the electric field is still very low in the middle of the drift region.…”

Section: Introductionmentioning

confidence: 99%

Novel high-voltage LDMOS with linear graded drift region width

Yao

Guo

Zhang

et al. 2015

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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In this paper, a novel Lateral Diffused Metal Oxide Semiconductor (LDMOS) with linear graded drift region width is proposed. The device features a specific drift region with the lateral width increasing from source to drain, which modulates the electric field distribution and increases the doping concentration. The breakdown voltage exceeds 600V on the proposed LDMOS with 1 m SOI layer, 3 m buried oxide and 60 m drift region length. The characteristics are investigated by a three dimensional simulator. The simulation results show that a 135% increase in breakdown voltage and 5 times increase in figure of merits are achieved for the proposed device when compared with those of the conventional device.

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Analytical models for the electric field distributions and breakdown voltage of Triple RESURF SOI LDMOS

Cited by 26 publications

References 8 publications

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

Novel high-voltage LDMOS with linear graded drift region width

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