Analytical Modeling and Performance Benchmarking of On-Chip Interconnects with Rough Surfaces

IET Computers & Digital Techniques

Sharma

2018

Self Cite

High-speed metal interconnects play a significant role in the on-chip network system as the network performance largely depends on the behaviour of these interconnects. Variability in wire properties due to the surface roughness directly impacts the overall system performance. In this study, the authors evaluate the effects of interconnect surface roughness on deeply scaled on-chip interconnects (i.e. 22, 13, and 7 nm) in the context of the network on chip (NoC). The critical roughness parameters of interconnect in NoC are extracted by atomic force microscopy analysis of fabricated thin sheets of copper. Their analysis shows that in a 5 × 5 NoC with 25 cores on 2.5 mm × 2.5 mm die, rough interconnects can lead to a significant penalty on energy budget, bandwidth density, bit error rate, the figure of merit and total system throughput. Their analysis shows that this penalty is further increased by moving towards interconnection lines at advanced technology nodes. They simulate the bodytrack workload of PARSEC benchmark by using Tejas Simulator to show the penalty on latency and energy of the architecture due to the rough interconnects. Their study makes an attempt to qualitatively and quantitative highlight the impact of the interconnect surface roughness on the design of power-aware NoCs.

Section: Results and Analysismentioning

confidence: 95%

Section: Surface Profile Function and Roughness Parameter Extractionmentioning

confidence: 99%

“…where m is the power spectra slope [10]. Similarly, we find out the roughness parameters for 13 and 22 nm technology nodes that are given in Table 1.…”

Section: Surface Profile Function and Roughness Parameter Extractionmentioning

confidence: 99%

“…p.u.l. of Cu interconnect with a rectangular crosssection and rough surfaces are derived in [8,10] and reproduced here:…”

Section: Interconnect Modelling With Surface Roughnessmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Investigating the role of interconnect surface roughness towards the design of power‐aware network on chip

IET Computers & Digital Techniques

Sharma

2018

Self Cite

Delay characterization of multilayer graphene nanoribbon interconnects in presence of scattering and thermal effects

Upadhyay

Int J Numerical Modelling

Khanna

2023

Scattering source‐based mean free path (MFP) and circuit modeling are proposed for three different configurations of undoped multilayer graphene nanoribbon (U‐MLGNR) (viz. horizontal top‐contact (HTC), horizontal side‐contact (HSC), and vertical top‐contact (VTC)). A similar analysis is carried out for doped HTC‐MLGNR (D‐HTC‐MLGNR) considering dopants viz. Li, FeCl3, and AsF5, for a temperature range of 300–500 K. The optimistic intrinsic‐phonon limited (Λeff,1(T)) and realistic scattering limited (Λeff,2(T)) effective MFP models are considered to derive the equivalent resistance of MLGNR. The performance of MLGNR variants, considering Λeff,1(T) and Λeff,2(T), is compared to copper (Cu) (with smooth and rough surface) in terms of coupled line crosstalk‐induced delay (XT‐D). The results show that the MLGNR variants outperform Cu interconnects in terms of XT‐D, for Λeff,1(T). However, structural edge roughness being the dominant scattering source in Λeff,2(T), severely degrades the performance of MLGNR variants in comparison to Cu counterparts. Moreover, for Λeff,1(T) and Λeff,2(T), Li‐D HTC‐MLGNR outperforms other MLGNR variants. Also, among the MLGNR variants, U‐VTC‐MLGNR exhibits a minimum average relative penalty of 21.58 × 102% in terms of XT‐D, when Λeff,2(T) is considered as against Λeff,1(T). Li‐D HTC‐MLGNR with optimized width exhibits 10.59× lower XT‐D and 8.85× higher XT‐D for Λeff,1(T) and Λeff,2(T), respectively, compared to smooth Cu. The optimized Li‐D HTC‐MLGNR demonstrates a reduction of 85.48% and 74.67% in XT‐D values for Λeff,1 (T) and Λeff,2 (T), respectively, when compared to mixed carbon nanotube (MCNT) bundle interconnects.

Analysis of Multilayer Graphene Nanoribbon Interconnects Constrained by Structural Edge Roughness and Corrugated Surface Dielectric

Upadhyay

Physica Status Solidi (a)

Khanna

2022

which can further degrade the interconnect performance. Hence, the increase in resistivity due to scaling is further aggravated by rough surfaces of Cu interconnect. [5,6] As a result of the issues faced by conventional Cu interconnects, researchers are on a quest to find a suitable candidate for very large scale integration (VLSI) on-chip interconnects. Cu-based materials like Cu-carbon nanotube (Cu-CNT) composite, [7] Cu-Graphene hybrid, [8] and Cu-Carbon hybrid [9] have been proposed as possible substitutes for Cu interconnects. Although, it is worth noting that the related fabrication of Cubased materials faces many challenges like achieving uniform CNT-Cu distribution, compatibility with complementary metal oxide semiconductor (CMOS) technology, and lack of a fully developed fabrication process. [7][8][9] In recent years, 1D carbonbased nanomaterials like CNTs and graphene nanoribbons (GNRs) are of significant interest in various applications like electronic devices, VLSI on-chip interconnects, through silicon via (TSVs) for 3D ICs, sensors, optics, medicine, mechanics, spintronics and energy storage devices, owing to their exceptional electronic, optical, thermal, and mechanical properties. [10][11][12] Moreover, both GNRs and CNTs show higher current densities, electrical and thermal conductivities than Cu. [13] Hence, researchers proposed GNRs and CNTs as emerging alternatives to conventional Cu for VLSI on-chip interconnects. [13][14][15][16] GNRs having planar structures are more consistent with the semiconductor industry's fabrication technology, [17,18] making GNRs preferable to CNTs.GNRs are classified into single-layer (SLGNR) and multilayer (MLGNR) GNR, where SLGNR with a single layer of GNR has very high intrinsic resistance. Hence, to achieve lower resistance and better performance, MLGNR is proposed in which multiple GNR layers are stacked on top of one another. [19,20] The MLGNRs can be further classified based on the contact formed between metal and MLGNR, i.e., top-contact (TC-MLGNR) and side-contact (SC-MLGNR) MLGNR. SC-MLGNR has lower resistance as all the layers are physically coupled to metal contacts, whereas only the topmost layer forms a connection with the metal contact in TC-MLGNR, leading to its inferior performance. However, in the present scenario, fabrication of TC-MLGNR is less challenging and practically feasible than SC-MLGNR. [19,20] TC-MLGNRs