Analytical Model of the Forward Operation of 4H-SiC Vertical DMOSFET in the Safe Operating Temperature Range

Abstract

A new analytical model of 4H-SiC DMOSFETs that is useful to explore their thermal stability is presented. The model is capable to describe, with closed form equations, the DC forward behavior of devices in a wide temperature range, including the effects of parasitic resistances and oxide interface traps. The model allows to analyze the on-set of electro-thermal stability of 4H-SiC DMOSFETs both in triode and in saturation region, and to monitor the impact of the series resistance and traps on reliable operation of devices. The accuracy of the model has been verified by comparisons with numerical simulations that evidence the effect of trap densities in the range [0-1014] cm-2eV-1 for operating temperatures up to 500K. Comparisons with experimental data of 1.2kV and 1.7kV commercial devices are used to validate the model

Impact of interface traps/defects and self‐heating on the degradation of performance of a 4H‐SiC VDMOSFET

“…On the other hand, when the temperature increases, the probability of re-emission will be higher, and the trapping will not occur [18]. The measurements of Licciardo et al [5] have shown a shift in the threshold voltage to the left when the operating temperature is increased. We have modelled the interface traps/defects as consisting of both donor and acceptor interface traps distributed in the energy.…”

“…In our device model, the deep level density of states distribution has been assumed to be Gaussian distributed. Accordingly, the total density of states is given by [5,14,19]…”

A Physics-Based Compact Model of SiC Power MOSFETs

“…The model in [12] uses an empirical function to describe the variation of the drain resistance with drain and gate voltage and with temperature. The model presented in [13] depends on parameters which are related to the manufacturing process. In [14] a resistance model is developed which is based on the modeling approaches for silicon DMOS transistors.…”

“…Recently some models have been published which try to consider the special effects occurring in SiC MOSFETs. Effects caused by interface traps are taken into account in [12] and [13]; [13] describes the influence of traps on the threshold voltage whereas [12] considers the variation of the electron mobility due to the traps. The variable drain resistance is modelled in [12]- [15]; a short discussion of these models is given in section II.B.…”

Failure Analysis of 1200-V/150-A SiC <sc>MOSFET</sc> Under Repetitive Pulsed Overcurrent Conditions

“…As a result of these improvements, overall system size is decreased yielding increased power densities with SiC MOSFETs compared to existing commercial systems utilizing Si IGBTs [9]. However, for SiC technology to displace the well-known and accepted Si devices, its performance and failure modes must be understood across all conditions expected in commercial applications [21]- [27]. Work has previously been performed to understand the effect of pulsed overcurrents on the long-term reliability of SiC MOSFETs [1], [24]; however, these results did not examine the failure mode, which must be analyzed through further testing and modeling.…”