Analytical I-V model and numerical analysis of single electron transistor

Abstract

The analytical I-V model of single electron transistor has been established and simulated by combining the Monte Carlo method with the Master Equation method. Effects of gate voltage, drain voltage, temperature, and tunneling junction resistance on electrical characteristics of a single electron transistor are analyzed. Simulation results indicate that for the device with symmetrical tunneling junction structure, the Coulomb staircases shift with increasing gate voltage, and the Coulomb oscillation amplitude increases with increasing drain voltage, while the Coulomb gaps decrease. The Coulomb staircases and the Coulomb oscillation disappear gradually with increasing temperature. The Coulomb blockade effects become more significant when the resistance ratio of the two asymmetrical tunneling junctions increases.

Annealing effect of platinum-incorporated nanowires created by focused ion/electron-beam-induced deposition

“…[3][4][5][6][7][8] The single electron transistor (SET) is one of the most investigated nanodevices in recent years. [9][10][11][12][13] The photolithography, electron-beam lithography (EBL), electronbeam evaporation, and lift-off procedures are commonly used techniques in SET production. As mentioned before, the dual beam system is a nano-lithography alternative, and some efforts have been made to investigate the SET using FIBID or FEBID techniques.…”