AnalyticalVTHandSmodels for (DMG–GC–stack) surrounding-gate MOSFET

Aouaj, Abdellah; Bouziane, Amal; Nouacry, A.

doi:10.1080/00207217.2011.589737

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…The use of GC, with two doping region highly doped region near source end and low doped region near drain end , showed significant improvement of hot carrier reliability and immunity against SCEs. Many works have also reported high-k dielectrics as an alternative to replace SiO2 as the gate dielectric In order to reduce gate leakage current and improve gate controllability over the channel [8,9].…”

Section: Introductionmentioning

confidence: 99%

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

Jaafar

Aouaj

Bouziane

et al. 2020

IJRES

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An Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surrounding-gate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS.

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Section: Introductionmentioning

confidence: 99%

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

Jaafar

Aouaj

Bouziane

et al. 2020

IJRES

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“…By solving 2D Poisson equation using parabolic approximation method, the expressions for surface potential, electric field, and threshold voltage are derived [9]. Subsequently, using device simulation and employing the analytical models [10], the reduction of SCE in DMG-GC-DOT MOSFET is presented. The results obtained are compared to results for (DMG) and (DMG-DOT) SG MOSFET.…”

Section: Introductionmentioning

confidence: 99%

Analytical and Numerical Modeling of Vth and S for New CG MOSFET Structure

Jaafar¹,

Aouaj²,

Bouziane³

2016

IJIST

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In this work, we study analytical model such threshold voltage (V TH ) and Subthreshold swing (SS) for a new Surrounding Gate MOSFET. This new SG-MOSFET is composed of Dual-metal Gate (DMG) M 1 and M 2 with different work function, Graded Channel (GC) whose the doping is higher near the source side than the drain side and Dual Oxide Thickness (DOT). Analytical model for V TH and SS are developed by solving 2D Poisson equation using parabolic approximation method. Results for new device are compared to those obtained by numerical simulation and have been found to be in good agreement. Comparative study between (DMG-GC-DOT) SG MOSFET and with different device engineering shows that the new structure provides improved electron transport and reduced short channel effects (SCE).

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“…The advantages of devices based on the SOI consist of the latch-up immunity of channel region, reduced short channel effects, higher transconductance and reduced parasitic capacitances. [1][2][3][4] Although many efforts have been performed to reduce the SCE with modifying the SOI based devices, [5][6][7][8][9][10][11][12] but there is a serious fabrication challenge for these devices. To benefit from the benefits of scaled SOI devices, it is imperative to make the source and drain region with a super steep doping profile that it is very difficult to realize it.…”

mentioning

confidence: 99%

Junctionless Transistor with Pulsed Shaped Dielectric (PSD-JNL): An Absorbing Structure for Nanoscale Aims

Anvarifard

2019

ECS J. Solid State Sci. Technol.

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Junctionless devices have been recently taken into consideration for the nanoscale applications. Regarding to the reliability weakness of the conventional Silicon-on-Insulator Junctionless (SOI-JLT) in nanoscale regime, this work has proposed a novel junctionless to overcome the basic problems occurring for it. The configuration of the buried oxide in the conventional JLT has been effectively modified with converting net SiO2 dielectric to a pulsed shaped dielectric including the silicon material and SiO2 material. The new configuration leaving a pulsed shaped dielectric as the buried oxide leads to the formation of an additional depletion layer in the channel region interface with the substrate. A meaningful result is that the effective channel width in the standby mode is reduced thus decreasing the leakage current, considerably. The comparisons in the cases of both DC and AC operations revealed that the proposed structure exhibits superior electrical performance in terms of the short-channel effects, thermal features, parasitic capacitance, transcondutance, output conductance, power gains, cutoff frequency, and minimum noise figure.

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AnalyticalV_THandSmodels for (DMG–GC–stack) surrounding-gate MOSFET

Cited by 5 publications

References 9 publications

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

Analytical and Numerical Modeling of Vth and S for New CG MOSFET Structure

Junctionless Transistor with Pulsed Shaped Dielectric (PSD-JNL): An Absorbing Structure for Nanoscale Aims

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