Analysis on Three‐Dimensional Gate Edge Roughness of Gate‐All‐Around Devices

Abstract

As the physical size of metal‐oxide‐semiconductor field effect transistor approaches the end of scaling down, the effect of process‐induced variations such as gate edge roughness on device performance cannot be neglected. For gate‐all‐around devices, the three‐dimensional gate profiles make the evaluation of gate edge roughness different and more complicated than that in planar metal‐oxide‐semiconductor field effect transistors. In this work, an evaluation algorithm was proposed to model the three‐dimensional gate edge roughness in a real gate‐all‐around device. The results show that the typical trapezoidal gate is more likely to suffer from gate edge roughness effect than the ideal rectangular gate. The effect of the size of the gate and the correlation coefficient of the edges on the effective channel length variation was also studied.

Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance

“…[8][9][10][11] In order to fulfill the demand for the higher effective width (W eff )/footprint ratios and better gate controllability to suppress the SCEs, vertically stacked horizontal gate-all-around (GAA) Si nanosheet field-effecttransistors (NSFETs) have been considered as one of the most promising candidates at 3 nm node and beyond. [12][13][14][15] The state-of-the-art process integration flow for GAA NSFETs enables full compatibility with traditional mainstream FinFETs and is expected to be introduced into mass production. 16 However, the bottom parastic "fat FinFETs" effect would lead to serious leakage current and large parasitic capacitance, which degrade the circuits performance and become one of the most significant challenges of NSFET devices.…”