Analysis of two FPGA design methodologies applied to an image processing system

Costas, Lucia; Colodron, Pablo; Rodríguez-Andina, Juan J.; Fariña, José; Chow, Mo-Yuen

doi:10.1109/isie.2010.5637828

Cited by 7 publications

(4 citation statements)

References 15 publications

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“…The memory demand of the histogram-based acceleration method is also high but is lower than that of the piecewise-linear approximation and subsampling approach. We choose an FPGA implementation for their image processing system because moving time critical functionalities, like the edge detection in an image, to hardware platforms makes it possible to keep delays in the control loop to a minimum [9]. [10] and [11] presents excellent experience of using FPGAs for motion control of robots based on real-time image processing.…”

Section: S Siddeswara Reddymentioning

confidence: 99%

Denoising of an Image using Bilateral Filter on FPGA

Pallavi¹,

Reddy²

2015

IJERT

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A bilateral filter for image processing is implemented on synchronous field programmable gate array. The reason for selecting bilateral filter is that it reduces noise while maintaining the details of the image and the design of bilateral filter is described on register transfer level. Our design concept consists of changing the clock domain in such a way that only one pixel clock cycle is required for the processing of the entire filter window i.e, kernel-based processing is performed. The main purpose of this kernel-based design is that it divides the input data into groups so that the internal clock of the design is a multiple of the pixel clock. Finally, the difficulty of the design is mostly reduced by making use of the separability and regularity of one filter component. By utilizing the dedicated resources effectively and economically the bilateral filter is implemented as highly parallelized pipeline structure. With low effort different sizes of kernels can be implemented because of the modularity of the filter design. Negligible quality loss of the output image is obtained due to the quantization of filter coefficients.

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Section: S Siddeswara Reddymentioning

confidence: 99%

Denoising of an Image using Bilateral Filter on FPGA

Pallavi¹,

Reddy²

2015

IJERT

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“…As this design methodology resembles to software development, it has been proven to lead to a similar degree of faults in the implementation [30]. However, modern design tools, like LabView FPGA [17], [31], DSP Builder [23] or System Generator [32], [33] are gaining momentum. It has been proven [32] that System Generator can lead to comparable results in terms of obtained speed as HDL description for complex designs.…”

Section: Simulink Modeling and Design Of An Efficientmentioning

confidence: 99%

“…However, modern design tools, like LabView FPGA [17], [31], DSP Builder [23] or System Generator [32], [33] are gaining momentum. It has been proven [32] that System Generator can lead to comparable results in terms of obtained speed as HDL description for complex designs. In [33], both the VHDL and the System Generator designs of an adaptive filter show similar performance in terms of speed and area.…”

Section: Simulink Modeling and Design Of An Efficientmentioning

confidence: 99%

Simulink Modeling and Design of an Efficient Hardware-Constrained FPGA-Based PMSM Speed Controller

Alecsa

Cirstea

Onea

2012

IEEE Trans. Ind. Inf.

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“…This approach significantly reduces design time, at the expense of obtaining non-optimized circuits. In case the performance of the resulting system is not good enough according to its specifications and requirements, it would be necessary to optimize the VHDL code [13].…”

Section: Fpga-based Implementationmentioning

confidence: 99%

Improving timing predictability in UGV control systems through FPGA implementation

Costas

Colodron

Ojha

et al. 2011

2011 IEEE International Symposium on Industrial Electronics

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In the design of network-based control systems, network delays and bandwidth variations must be carefully taken into account. In order for the performance of these systems to be optimized, it is necessary to minimize loop delay predictable as possible. In this work, an FPGA proposed to improve predictability, while at the same time reducing loop delay, in a control system for Unmanned Ground Vehicles in the context of an intelligent space Experimental results are presented demonstrating the significant improvements that can be achieved with regard to the existing PC-based solution. Future improvements that can be obtained from the use of advanced features and resources of also identified.

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Analysis of two FPGA design methodologies applied to an image processing system

Cited by 7 publications

References 15 publications

Denoising of an Image using Bilateral Filter on FPGA

Denoising of an Image using Bilateral Filter on FPGA

Simulink Modeling and Design of an Efficient Hardware-Constrained FPGA-Based PMSM Speed Controller

Improving timing predictability in UGV control systems through FPGA implementation

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