Analysis of the dV/dt effect on an IGBT gate circuit in IPM

Abstract

The effect of dV /dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV /dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV /dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV /dt induced self turn-on. By optimizing these parameters, the dV /dt induced voltage spike can be effectively controlled.

Highly Integrated DBC-Based IPM with Ultra-Compact Size for Low Power Motor Drive Applications

“…At the beginning of the design, the relevant parameters of the highly Fig. 8 Input voltage and output current waveforms of the highly integrated IPM at working frequency of 75 Hz integrated IPM are design compatible with the traditional solutions [18]- [21]. The above experimental results also confirm this point.…”

A Temperature-Dependent dVCE/dt Model for Field-Stop IGBT at Turn-Off Transient

“…Moreover, the steep dV CE /dt can capacitively couple into the gate through the gate-collector stray capacitances, which induces a displacement current. The displacement current generates a voltage on gate loop impedance, which drive the gate to increase [6], [7]. When the dV CE /dt is high enough, the gate voltage can surpass the threshold voltage and causes unwanted false turnon.…”