Analysis of subthreshold leakage reduction in CMOS digital circuits

Deepaksubramanyan, B.S.; Nunez, A.

doi:10.1109/mwscas.2007.4488809

Cited by 72 publications

(39 citation statements)

References 6 publications

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“…Their contribution to the overall power consumption is rather limited but still not negligible ( 10-30%), except for very low voltages V dd ≤ V tn +│V tp │, where the shortcircuit currents disappear. A low-power logic style should have minimal short-circuit currents and of course, no static currents besides the inherent CMOS leakage currents [13]. Components of static power dissipation are junction leakage, sub-threshold leakage, gate-oxide leakage, gate induced drain leakage, punch through leakage and hot carrier injection.…”

Section: Short Circuit Power Dissipationmentioning

confidence: 99%

“…The dynamic power ( ) occurs due to the change in logic state results charging and discharging of output load capacitance. The short circuit power ( ℎ − ) dissipates when both pMOS and nMOS transistors of CMOS circuits partially ON (short-circuited) for very short duration during switching [12][13][14]. At the circuit level, large differences are primarily observed between static and dynamic logic styles.…”

Section: Short Circuit Power Dissipationmentioning

confidence: 99%

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A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

Rathore¹,

Kumre²

2017

IJCA

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In the continuous scaling down of technology in the field of integrated circuits, low power circuits are in demand for reliability and performance. This research focuses on run time leakage reduction technique for CMOS devices, this work introduces two well known approaches, stack approach with pass transistor approach for reduction of the leakage power and improves the performance of the circuit. Here NMOS transistor and PMOS transistor parallel to each other in between pull up and pull down network, the resistance is increased by providing stacking of the transistor for mitigation of leakage power. For proper validation and verification of results we use the module of proposed NAND gate to built a Full Adder circuit and for verification of results. Here NMOS pass transistor is connected between pull up network and pull down network similarly PMOS transistor is also connected between pull up network and pull down netwotk both NMOS and PMOS pass transistor are self controlling transistor whch reduces the power consumption in active and ideal mode at 43.33%, 43.33%, 86.07% and 86.04% at 25oC respectively as compared with the standard 2 input NOT,AND,NAND and NOR gates. Average dynamic power is reduced to 14.34%, 14.34%, 34.69%, 30.68% respectively.

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Section: Short Circuit Power Dissipationmentioning

confidence: 99%

Section: Short Circuit Power Dissipationmentioning

confidence: 99%

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

Rathore¹,

Kumre²

2017

IJCA

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show abstract

“…The zigzag technique reduces the overhead by choosing a particular circuit state (e.g., corresponding to a "reset") and then, for the exact circuit state chosen, turning off the pull-down network for each gate whose output is high while conversely turning off the pull-up network for each gate whose output is low [10]. If the output is "1," then a pull-down sleep transistor is applied; if the output is "0," then a pull-up sleep transistor is applied.…”

Section: Zigzag Techniquementioning

confidence: 99%

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Alekhya¹,

Sudhakar²

2017

IOSR JVSP

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“…The majority of the power dissipated in an integrated circuit is due to dynamic activity: net switching power, internal cell power and short-circuit power during logic transitions in the Complementary Metal-Oxide-Semiconductor (CMOS) transistors [1]. But the proportion of static power, also called leakage power, is approaching half of all power consumed in an ASIC as the contemporary technology node libraries keep advancing towards ever smaller line widths [2].…”

Section: Power Consumptionmentioning

confidence: 99%

“…The majority of the power dissipated in an integrated circuit is due to dynamic activity: net switching power, internal cell power and short-circuit power during logic transitions in the transistors [1]. However, the proportion of static power dissipation, also known as leakage power, is quickly growing towards half of all power used as the deep submicron technology nodes continue to decrease in size [2]. The smaller the technology, the more leakage will be present.…”

Section: Introductionmentioning

confidence: 99%

Variable length instruction compression on Transport Triggered Architectures

Helkala

Viitanen

Kultala

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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The Static Random-Access Memory (SRAM) modules used for embedded microprocessor devices consume a large portion of the whole system's power. The memory module consumes static power on keeping awake and dynamic power on memory accesses. The power dissipation of the instruction memory can be limited by using code compression methods, which reduce the memory size. The compression may require the use of variable length instruction formats in the processor. The powerefficient design of variable length instruction fetch and decode units is challenging for static multiple-issue processors, because such architectures have simple hardware to begin with, as they aim for very low power consumption on embedded platforms. The power saved by using these compression approaches, which necessitate more complex logic, is easily lost on inefficient processor design.This thesis proposes an implementation for instruction template-based compression, its decompression and two instruction fetch design alternatives for variable length instruction encoding on Transport Triggered Architecture (TTA), a static multiple-issue exposed data path architecture. Both of the new fetch and decode units are integrated into the TTA-based Co-design Environment (TCE), which is a toolset for rapid designing and prototyping of processors based on TTA.The hardware description of the fetch units is verified on a register transfer level and benchmarked using the CHStone test suite. Furthermore, the fetch units are synthesized on a 40 nm standard cell Application Specific Integrated Circuit (ASIC) technology library for area, performance and power consumption measurements. The power cost of the variable length instruction support is compared to the power savings from memory reduction, which is evaluated using HP Labs' CACTI tool.The compression approach reaches an average program size reduction of 44% at best with a set of test programs, and the total power consumption of the system is reduced. The thesis shows that the proposed variable length fetch designs are sufficiently low-power oriented for TTA processors to benefit from the code compression.

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Analysis of subthreshold leakage reduction in CMOS digital circuits

Cited by 72 publications

References 6 publications

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Variable length instruction compression on Transport Triggered Architectures

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