Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs

Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness

“…Our own analysis of SEM micrographs of resist lines obtained from EUV [15] and e-beam [17] lithography indicates values of in the range of 20-30 nm. Gaussian and exponential power spectral models are found to perform almost equally well as least square fits to the captured autocorrelation data [11] as shown in Fig. 3.…”

“…Various sources of intrinsic parameter fluctuations have been studied using numerical simulations with a preference given in the past to random discrete dopants in the active region of the transistor [5]- [7], random dopants and grain boundaries in the polysilicon gate [8] and oxide thickness fluctuations [9]. The line edge roughness (LER) caused by tolerances inherent to materials and tools used in the lithography processes is yet another source of intrinsic parameter fluctuations [10], [11] which needs close attention. LER has caused little worry in the past since the critical dimensions of MOSFETs were orders of magnitude larger than the roughness.…”

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

“…The line edge roughness (LER) caused by tolerances inherent to materials and tools used in the lithography processes is yet another source of intrinsic parameter fluctuations [95], [96], which needs close attention. LER has caused little worry in the past since the critical dimensions of MOSFETs were orders of magnitude larger than the roughness.…”

“…As a natural extension to the statistical 3-D simulations methodology, the simulation of LER in decananometer MOSFETs was approached in a coherent statistical fashion in [96], [106]. The LER in the simulations is specified by rms amplitude and correlation length .…”

Monte Carlo Simulation of SEM and SAM Images

“…Among them, however, the influence of the side wall roughness, the line edge roughness (LER) or the line width roughness (LWR), to CDs has rarely been included in a theoretical calculation because of the complexity of constructing a reasonable rough surface model. The LER or the LWR can degrade resolution and linewidth accuracy (Yoshimura et al, 1993) and cause fluctuation of transistor performance (Asenov et al, 2003;Croon et al, 2002;Diaz et al, 2001;Ercken et al, 2002;Hamadeh et al, 2006;Kaya et al, 2001;Kim et al, 2004a;Kim et al, 2004b;Linton et al, 1999;Linton et al, 2002;Oldiges et al, 2000;Xiong & Bokor, 2002;Yamaguchi et al, 2003;Yamaguchi et al, 2004). It becomes a critical issue when the CDs for semiconductor devices shrink into few tens nanometers (ITRS, 2007;Gwyn et al, 2003) because the roughness on the edge of the line does not scale with the linewidth (Asenov et al, 2003).…”