Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

Voldman, Steven H.; Gerosa, G.; Gross, V.; Dickson, Nicholas; Furkay, S.; Slinkman, J.

doi:10.1109/eosesd.1995.478267

Cited by 54 publications

(27 citation statements)

References 18 publications

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“…For negative HV signal, the current goes through PNP BPTs to ground. A similar scheme has been used to protect the chip from the electrostatic discharge phenomenon [7]. Fig.…”

Section: The Limiter Architecturesmentioning

confidence: 99%

Bipolar-power-transistor-based limiter for high frequency ultrasound imaging systems

2014

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High performance limiters are described in this paper for applications in high frequency ultrasound imaging systems. Limiters protect the ultrasound receiver from the high voltage (HV) spikes produced by the transmitter. We present a new bipolar power transistor (BPT) configuration and compare its design and performance to a diode limiter used in traditional ultrasound research and one commercially available limiter. Limiter performance depends greatly on the insertion loss (IL), total harmonic distortion (THD) and response time (RT), each of which will be evaluated in all the limiters. The results indicated that, compared with commercial limiter, BPT-based limiter had less IL (–7.7 dB), THD (–74.6 dB) and lower RT (43 ns) at 100MHz. To evaluate the capability of these limiters, they were connected to a 100 MHz single element transducer and a two-way pulse-echo test was performed. It was found that the -6 dB bandwidth and sensitivity of the transducer using BPT-based limiter were better than those of the commercial limiter by 22 % and 140 %, respectively. Compared to the commercial limiter, BPT-based limiter is shown to be capable of minimizing signal attenuation, RT and THD at high frequencies and is thus suited for high frequency ultrasound applications.

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“…For negative HV signal, the current goes through PNP BPTs to ground. A similar scheme has been used to protect the chip from the electrostatic discharge phenomenon [7]. Fig.…”

Section: The Limiter Architecturesmentioning

confidence: 99%

Bipolar-power-transistor-based limiter for high frequency ultrasound imaging systems

2014

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“…The ESD design considerations include the voltage turn-on condition, the resistance, and the leakage amplification issue. The leakage amplification was discussed by S. Dabral and T. J. Maloney [4][5][6], and G. Gerosa and S. Voldman [7,8]. In the implementation by Gerosa and Voldman, a simple diode was implemented across a number of successive stage to limit the forward bias diode turn-on [7,8].…”

Section: Esd Power Clamps: Series Diode Strings As Core Clamps-claddementioning

confidence: 99%

“…The successive diode stages are in a pnp common-collector configuration. As was shown for mixed voltage interface (MVI) dual-well CMOS diode strings, the leakage is amplified by each successive stage [5][6][7][8][9]. Triple-well CMOS and BiCMOS technologies allows for a buried n-type layer to be placed in a fashion to isolate the p-epitaxial region or p-well region [10].…”

Section: Esd Power Clamps: Triple-well Series Diodes As Core Clampsmentioning

confidence: 99%

“…ESD power clamps popularity occurred in the 1990s to achieve better ESD results in semiconductor chips [1][2][3][4][5][6]. By mid 1990s, diode string [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], 3,[20][21][22][23][24][25][26][27], and bipolar ESD power clamps [43][44][45][46][47][48][49], and silicon-controlled rectifiers [50-60] became part of the ESD design methodology and practice. From 1995 to 2005, the focus on the MOSFET ESD power clamps have been on producing a better ESD power clamp, design integration, physical placement [33][34][35][36], and low leakage [38].…”

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ESD Power Clamps

2005

Esd

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An electrostatic discharge (ESD) design practice is the integration of ESD power clamps between the power supply rails. ESD power clamps popularity occurred in the 1990s to achieve better ESD results in semiconductor chips [1][2][3][4][5][6]. By mid 1990s, diode string [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], 3,[20][21][22][23][24][25][26][27], and bipolar ESD power clamps [43][44][45][46][47][48][49], and silicon-controlled rectifiers [50-60] became part of the ESD design methodology and practice. From 1995 to 2005, the focus on the MOSFET ESD power clamps have been on producing a better ESD power clamp, design integration, physical placement [33][34][35][36], and low leakage [38]. In the other technologies, the focus has been extending the concepts to triple-well CMOS [11,12], BiCMOS, silicon germanium [10,[13][14][15][45][46][47], gallium arsenide [48,49], and silicon-oninsulator (SOI) technologies [17][18][19]. ESD power clamps achieve both functional and ESD advantages. ESD power clamps achieve ESD robustness and electrical overstress (EOS) robustness by enhancing the ESD design practice as follows:Establishment of ESD Current Loops: The addition of power clamps provides an alternative current loop for the ESD current.Bidirectional Current Paths: Bidirectional current flow allows the flow of the ESD current through the loop in both directions.Segmented Chip Current Path: ESD power clamps can be placed between independent and disconnected chip segments allowing electrical connectivity.Rail-to-Rail ESD Protection: Rail-to-rail ESD protection between the two power rails is achieved using the power clamp placed between the two power rails.Pin-to-Pin ESD Protection: Pin-to-Pin ESD protection is achieved by establishing bidirectional current paths from the first pin, through the power clamp and to the second pin. ESD: Circuits and Devices Steven H. Voldman

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“…With mixed-voltage applications, new OCD networks need to satisfy this condition [8][9][10][11][12][13][14][15][16][22][23][24]. Additionally, the introduction of multiple power supply voltage levels within a chip introduced complexity in the chip architecture, bussing, sequencing, and ESD protection schemes [17][18][19][20][21].…”

Section: Off-chip Drivers: Mixed-voltage Interfacementioning

confidence: 99%

Off‐Chip Drivers (OCD) and ESD

Voldman

2005

Esd

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Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

Cited by 54 publications

References 18 publications

Bipolar-power-transistor-based limiter for high frequency ultrasound imaging systems

Bipolar-power-transistor-based limiter for high frequency ultrasound imaging systems

ESD Power Clamps

Off‐Chip Drivers (OCD) and ESD

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