Analysis of Single Halo Double Gate MOSFETs using high-k dielectrics

Abstract

Double-gate (DG) MOSFETs came into popularity because of its excellent scalability and better immunity to Short Channel Effects. They are used for CMOS applications beyond the 70 nm node of the SIA roadmaap. However DG devices with channel lengths below 100nm show considerable leakage current and threshold voltage roll off. In this paper, we investigate the influence of channel engineering on the performances of Double Gate (DG) MOSFETs using high-k dielectrics for system-on-chip applications. A Single Halo Double Gate (SH DG) MOSFET is simulated using 2D device simulator and performance is analysed for parameters such as Early voltage, electron velocity and electron mobility. The impact of high-k gate dielectrics on the device short channel performance is studied over a wide range of dielectric permittivity. The device shows 20% increase in drain current as compared to conventional MOSFET. The integration of high-k gate dielectrics further enhances the performance. Drain current increases by 28% and early voltage increases by 34% as the dielectric value increases. The electron velocity also increases with increasing dielectric value.

Effect of High-k Dielectric Materials on Short Channel Effects of a 14 nm Tri-Gate SOI FinFET for Reduced Area on Chip

“…Improvements in Ion, Ioff and Ion/Ioff for the device with HfO2 high-k dielectric are observed. The Ion/Ioff ratio obtained for HfO2 (k = 25) is 1.3510 6 and SiO2 (k = 3.9) is 2.7710 5 . Similarly, the SCEs like subthreshold swing and DIBL also showed improved results for the FinFET with HfO2 as a dielectric material.…”

“…This concept thereby stands as the core of the paper here. The high-k dielectric material increases the gate capacitance without the leakage effects and increases the Ion current [5]. The choice of a high-k dielectric material also depends on its ability to provide acceptable level of leakage as well as improved mobility of the charge carriers.…”

Nanoscale channel engineered double gate MOSFET for mixed signal applications using high‐k dielectric

“…Figure shows that the electron velocity in the halo region is 7.5 x 10 6 um/s which is lesser when compared to the velocity in the channel region because of the increased number of dopants. The electron velocity increases with the dielectric constant, and this increase is more prominent in the halo‐doped region, thereby improving the carrier transport efficiency of the device . Figure shows the lateral electric field variation along the channel position.…”

“…The reduction of threshold voltage with decreasing channel length and increasing drain voltage is widely used as an indicator of the Short Channel Effect (SCEs) in evaluating CMOS cutting‐edge technologies. This adverse threshold voltage roll‐off effect is the most daunting road block in future metal–oxide–semiconductor (MOS)FET design . The minimum acceptable channel length is primarily determined by this roll‐off.…”