Analysis of Self-Heating-Related Instability in Self-Aligned p-Channel Polycrystalline-Silicon Thin-Film Transistors

Abstract

Self-heating-related instabilities have been studied in p-channel polycrystalline-silicon thin-film transistors. The spatial distribution of the interface-state and fixed-oxide-charge densities generated during self-heating experiments has been analyzed and quantitatively determined by using negative-bias temperature stress experiments and 2-D numerical simulations. In addition, the observed asymmetry in the output characteristics with respect to source/drain contact reversal is also perfectly reproduced, confirming the validity of the proposed model.

Edge Effects in Self-Heating-Related Instabilities in p-Channel Polycrystalline-Silicon Thin-Film Transistors

“…1 shows the bias-stress results, performed in devices with different channel lengths L in the SH regime under constant power density (0.04 mW/µm 2 ) for the same V g − V t = −12.2 V and high V ds and for a bias-stress time of up to 1000 s. As can be noted, the V T shift after 1000 s of bias stress was increasing for increasing L (∆V T = −4.5, −5.9, and −8.7 V for L = 1, 2, and 6 µm, respectively), and the devices with L = 2 and 6 µm show a g m overshoot, after bias stress, which instead is not observed in the short-channel device (L = 1 µm). It should be pointed out that, when performing a thermal annealing at T > 180 • C before bias-stress experiments, the g m overshoot is not observed [3]. In addition, we have also reported that bias stress under NBTI conditions can also produce a g m overshoot, similar to the g m overshoot induced by bias stressing in the SH regime [4].…”

“…However, Fuyuki et al [6] have recently shown that the V T shift observed in devices with different grain sizes bias-stressed in the SH regime follows a universal temperature-dependent curve, suggesting that device degradation does not depend on grain boundary traps. In addition, as shown by Gaucci et al [3], the effects of NBTI and of SH-related instability in polysilicon TFTs can be perfectly reproduced using numerical simulations by simply introducing additional interface states and fixed oxide charge, without the need of extra bulk traps. Therefore, we have assumed that device degradation is mainly due to the generation of interface states and fixed oxide charge, commonly attributed to the breaking of the Si-H bonds at the Si/SiO 2 interface [5].…”

“…Normally, bias-stress experiments performed in the SH regime on p-channel polysilicon TFTs produce an increase in the threshold voltage (V T ) and a degradation of the subthreshold slope, while transconductance (g m ) is not appreciably changed [1]- [3]. These effects can be, in general, attributed to the generation of interface states and positive fixed oxide charge [3], in analogy to negative bias temperature instability (NBTI) in c-Si MOSFETs [5], and to the creation of additional grain boundary traps [2]. However, Fuyuki et al [6] have recently shown that the V T shift observed in devices with different grain sizes bias-stressed in the SH regime follows a universal temperature-dependent curve, suggesting that device degradation does not depend on grain boundary traps.…”

Polysilicon thin-film transistors on polymer substrates

“…Hence, given identical performance values, TFTs used in the flexible microelectronics exhibit greater susceptibility to selfheating than do TFTs used in the current glass-based liquid crystal displays (LCDs) [30,51,52]. When LTPS TFTs are operated in the SH regime, the device characteristics of both n-and p-channel devices are degraded [30,[53][54][55], showing an increase in the threshold voltage (V T ) and a degradation of the subthreshold slope. These effects can be, in general, attributed to the generation of interface states and positive fixed oxide charge [54], due to the breaking of the Si-H bonds at the Si/SiO 2 interface and within the SiO 2 close to the interface [56].…”

“…When LTPS TFTs are operated in the SH regime, the device characteristics of both n-and p-channel devices are degraded [30,[53][54][55], showing an increase in the threshold voltage (V T ) and a degradation of the subthreshold slope. These effects can be, in general, attributed to the generation of interface states and positive fixed oxide charge [54], due to the breaking of the Si-H bonds at the Si/SiO 2 interface and within the SiO 2 close to the interface [56]. In addition, when the device temperatures approach the glass transition temperatures of the polymer substrates, TFTs can be also damaged by the thermal deformation of the plastic material.…”