2020
DOI: 10.1109/ted.2020.3013564
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Analysis of RF Inductive Effect in S-Parameters of Body Contact PD-SOI MOSFETs

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Cited by 5 publications
(3 citation statements)
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“…Physically L k is generated by the negative output capacitance 8 due to a substrate current‐induced body effect (SCBE) in BCT PD‐SOI nMOSFETs and expressed by the following Equation ) at f p ≪ f ≪ f r where f p = (1/ R bi + g bs )/[2 π ( C bs + C bd )]: 8 LkCbs+Cbdgii(gmb+gmp) where f p is the pole frequency of g ds , R bi is the intrinsic body resistance, C bd is the body‐drain junction capacitance, C bs is the body‐source capacitance, g bs is the dynamic body‐source conductance, g mb is the body transconductance, g mp is the transconductance for parasitic BJT, and g ii is the transconductance for impact ionization current.…”
Section: Modeling and Parameter Extractionmentioning
confidence: 99%
See 1 more Smart Citation
“…Physically L k is generated by the negative output capacitance 8 due to a substrate current‐induced body effect (SCBE) in BCT PD‐SOI nMOSFETs and expressed by the following Equation ) at f p ≪ f ≪ f r where f p = (1/ R bi + g bs )/[2 π ( C bs + C bd )]: 8 LkCbs+Cbdgii(gmb+gmp) where f p is the pole frequency of g ds , R bi is the intrinsic body resistance, C bd is the body‐drain junction capacitance, C bs is the body‐source capacitance, g bs is the dynamic body‐source conductance, g mb is the body transconductance, g mp is the transconductance for parasitic BJT, and g ii is the transconductance for impact ionization current.…”
Section: Modeling and Parameter Extractionmentioning
confidence: 99%
“…Recently, it has been reported that S 21 ‐ and S 22 ‐parameters in BCT PD‐SOI nMOSFETs at the kink bias rotate clockwise in the lower and upper half circles of Smith chart, 8 respectively, as the frequency increases. This anomalous RF kink effect is similar to the inductive effect measured in S 22 ‐parameter of bulk MOSFETs biased in the breakdown region 9 …”
Section: Introductionmentioning
confidence: 99%
“…Owing to the low-temperature and low-cost processes, polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) have been extensively studied for applications to large area electronics and 3D stackable circuits. [1][2][3][4][5][6][7] One of the problems in the TFTs is their relatively low mobility as compared with the bulk Si counterparts. In poly-Si, the grain boundaries can form charge trapping sites that are capable of creating a potential barrier, leading to the reduction of the effective channel mobility.…”
Section: Introductionmentioning
confidence: 99%