Analysis of OPC optical model accuracy with detailed scanner information

Zavyalova, Lena; Lucas, Kevin; Zhang, Qiaolin; Fan, Yongfa; Sethi, Satyendra S.; Song, Hua; Tyminski, Jacek K.

doi:10.1117/12.774116

Cited by 7 publications

(4 citation statements)

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“…For 22nm (PTM HP v2.1) the nMOS sized as explained in Section IV (see 29) to is gives the SNM ulations for 22nm OS = 25.3nm, and larger than those ncrements can be [8], [19]. e symmetrical) for ds when one gate for all single input of NAND-2, and e cases when both inputs are changing simultaneously script was used to calculate the SNM in [5] SNM's were determined from gain), here we have used the maxim is the most accurate one [4].…”

Section: Simulation Resultsmentioning

confidence: 99%

On upsizing length and noise margins

Beiu

Tache

Ibrahim

et al. 2013

CAS 2013 (International Semiconductor Conference)

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This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (V th ) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that V th and L change by ~2%, while SNM's increase by ~30%, with power and energy being reduced ~10× and ~20× respectively.

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Section: Simulation Resultsmentioning

confidence: 99%

On upsizing length and noise margins

Beiu

Tache

Ibrahim

et al. 2013

CAS 2013 (International Semiconductor Conference)

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“…Exact calculations for 22nm (PTM HP v2.1), give L opt_nMOS = 25.3nm, and L opt_pMOS = 29.8nm, which are just 0.4nm larger than those estimated in [5]. We shall call this the 2L-OPT sizing method as requiring two different values for L. Sizing in very small increments can be envisaged using optical proximity correction [8], [19]. Similarly, we have used eqs.…”

Section: Maximizing the Static Noise Marginsmentioning

confidence: 98%

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Kharbash

Beiu

Tache

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (V th ) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (V bs ) for having a single L opt for all transistors (as opposed to having two different L opt , one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although V th and L change by ~10%, by using V bs we can still achieve very high SNM's, while additionally reducing power and energy to ~50%.

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“…Sizing in very small increments (e.g. even below 1 nm) could be envisaged by relying on the optical proximity correction as suggested in [71, 72]…”

Section: Unconventional Sizing For Enhancing Reliabilitymentioning

confidence: 99%