Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array

Kumar, Saurabh; Cho, Minki; Everson, Luke; Tang, Qianying; Meinerzhagen, Pascal; Malavasi, Andres; Lake, Dan; Tokunaga, Carlos; Khellah, Muhammad; Tschanz, James; De, Vivek; Kim, Chris H.

doi:10.1109/tns.2019.2911540

Cited by 10 publications

(5 citation statements)

References 23 publications

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“…Consequently, in Fig. 8, we present results for the patterns observed in [11] as well as for the same patterns without horizontal/diagonal MCU, only vertical MCUs (the four right-most columns-that capture better the strength of the proposal in our paper).…”

Section: Rtd Impact On Soft-error Rate (Ser)mentioning

confidence: 96%

“…In this paper, we show how to implement RTD for a F/F based array. Such arrays are popular in modern CPUs [11]. F/F arrays with size up to a few thousand bits are known to offer area and power advantages over equal-size SRAM-based arrays [12][13].…”

Section: Rtd Applicability and Implementationmentioning

confidence: 99%

“…SBU (Single Bit Upsets) are the most dominant SER fault type but multi-bit upsets (MBUs) also happen occasionally -and they are increasing in smaller technology nodes [20]. In [11], authors analyze MBUs in a 14nm FinFET-based F/F array subject to neutron radiation and they observed eleven different fault patterns of MBUs. MBUs of up to 4 bits bursts are observed in F/F arrays.…”

Section: Rtd Impact On Soft-error Rate (Ser)mentioning

confidence: 99%

“…The F/F array evaluated in [11] does not include: i) the logic column for a normal read access of the data; ii) the column for to read the value to overwrite; and iii) the column that calculates the real time column parity. These columns may present an "isolation" for a single-event to cause multiple faults in the horizontal/diagonal direction.…”

Section: Rtd Impact On Soft-error Rate (Ser)mentioning

confidence: 99%

See 3 more Smart Citations

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

Sazeides

Bramnik

Gabor³

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use in-line error-detection and correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper presents how to build RTD into a memory array with flip-flops to track in real-time the column-parity and introduces a twodimensional Error-Correction scheme based on RTD. As compared to SECDED, the evaluated scheme has comparable error detection and correction strength and, depending on the array dimensions, the access time is reduced by 8% to 24% at an area and power overhead between 12% to 53% and 21% to 42% respectively.

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Section: Rtd Impact On Soft-error Rate (Ser)mentioning

confidence: 96%

Section: Rtd Applicability and Implementationmentioning

confidence: 99%

Section: Rtd Impact On Soft-error Rate (Ser)mentioning

confidence: 99%

Section: Rtd Impact On Soft-error Rate (Ser)mentioning

confidence: 99%

See 2 more Smart Citations

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

Sazeides

Bramnik

Gabor³

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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show abstract

“…To tolerate soft errors in the device level, many storage cells, such as latches [2][3][4][5][6][7][8][9][10][11][12], SRAMs [13][14], and flip-flops [15][16], have been proposed. This paper focuses on latch designs.…”

Section: Introductionmentioning

confidence: 99%

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

Yan

Cui

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to chargesharing-induced multiple-node-upsets (MNUs) in harsh radiation environments. Muller C-elements are widely used for latch hardening against MNUs, such as triple and even quadruple node-upsets. Existing latch verifications for error-recovery highly rely on EDA tools with complex error-injection combinations. In this paper, a latch design with algorithm-based verification protected against MNUs in harsh radiation environments, is proposed. Due to the formed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification results demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing same-type design.

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Fault tolerant micro-programmed control unit for SEU and MBU mitigation in space based digital systems

S.,

2024

Microelectronics Reliability

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Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array

Cited by 10 publications

References 23 publications

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

Fault tolerant micro-programmed control unit for SEU and MBU mitigation in space based digital systems

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