Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

Hung, Wei‐Ting; Jin, Fu‐Yuan; Chang, Ting‐Chang; Hung, Wei‐Chun; Chang, Chin-Han; Chang, Kai‐Chun; Yeh, Chien‐Hung; Kuo, Ting-Tzu; Hsu, J.Y.; Lee, Ya-Huan; Huang, Jen‐Wei

doi:10.1109/tdmr.2023.3263868

Cited by 2 publications

(4 citation statements)

References 24 publications

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“…The process of the mini-LOCOS field plate is the most critical process [16,17]. It can be divided into six steps:…”

Section: Methodsmentioning

confidence: 99%

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

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“…The process of the mini-LOCOS field plate is the most critical process [16,17]. It can be divided into six steps:…”

Section: Methodsmentioning

confidence: 99%

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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“…It can be seen when L increase from 0.3 μm to 0.55μm, the depletion region increase obviously , while the depletion boundary keeps nearly no change from L= 0.55μm to L=0.65μm. Since the current path length , which is discussed in Section II, part C, is proportional to the depletion region, the result consists of equation (2)(3)(4)(5)(6). The reason for limitation at L=0.55μm is due to depletion region limitation, which is considered related to drift/body concentration, and another possible reason is that the current path length is not circular again at higher drift region.…”

Section: B Field Plate Length-l Effectsmentioning

confidence: 99%

“…ecently, BCD (Bipolar-CMOS-DMOS) circuits based on LDMOS (Lateral double diffusion metal oxide semiconductor) devices have been widely applied in PMICs (Power management integrated), IoT (Internet of things), AI (Artificial intelligence), and automotive owing to its advantages of high speed and easy integration [1][2] [3]. In the device structure design and process integration of LDMOS, field plate technology is the most critical technology widely used for source-drain (Breakdown voltage) improvement [4][5] [6]. An appropriate field plate structure could produce a uniform distribution of the electric field in the drift region by reducing the surface peak electric field and increasing the lateral electric field, thereby increasing the device's .…”

Section: Introductionmentioning

confidence: 99%

“…At present, the field plate commonly used in the IC (Integrated circuit) manufacturing industry are two structures: mini-STI (Shallow trench isolation) field plate and mini-LOCOS (Local oxidation of silicon) field plate [6] [7]. Many new researchers have been published [8] [9][10] [11] [12], and they focus on optimizing and innovating field plate structures in LDMOS devices.…”

Section: Introductionmentioning

confidence: 99%

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Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low , (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length L, field plate thickness H, and slot contact width W, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that , can achieve as low as 6.9m•mm 2 when the source-drain (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W=10 m) and very large devices (W= 2mm). Index Terms-Contact field plate (CFP), Figures of merits (FOM), Lateral double diffusion metal oxide semiconductor (LDMOS), Specific on-resistance ( , )

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Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

Cited by 2 publications

References 24 publications

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

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