Analysis of Gate Misalignment Effects in Double Gate Junctionless MOSFET

Jana, Gargi; Majumdar, Madhuchhanda; Chanda, Manash; Sarkar, Chandan Kumar

doi:10.1109/icacct.2018.8529631

Cited by 2 publications

(2 citation statements)

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“…The fabrication of DG structure with perfectly aligned gate electrodes has been a critical issue in sub-100 nm regimes [18][19][20][21][22]. The effect of gate misalignment on the subthreshold characteristics and various analog/RF parameters of various junction-based and junctionless DG FETs has been presented in the literature [23][24][25][26][27][28][29][30][31][32]. It has been shown that misalignment primarily impacts the electrostatic strength of gate electrodes in the channel region which results in degraded subthreshold performance [23][24][25][26][27][28][29].…”

Section: Introductionmentioning

confidence: 99%

“…However, it has been noticed that most of these studies focusing on the effect of gate misalignment have been limited to investigating the subthreshold characteristics and/or analog/radio frequency (RF) performance parameters for different junctionless and junction-based FET structures [23][24][25][26][27][28][29][30][31][32]. To the best of our knowledge, the impact of gate misalignment in digital/analog circuits has yet not been studied extensively.…”

Section: Introductionmentioning

confidence: 99%

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Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

Kumar¹,

Chatterjee²,

Pandey³

2022

Semicond. Sci. Technol.

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In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2-D Silvaco ATLAS TCAD. With recessed silicon channel, the quantum confinement effects have been considered for channel thickness < 7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope, and lower drain-induced-barrier-lowering. Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of subthreshold slope and drain-induced-barrier-lowering with smaller variations of ~10.84% and ~61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different AC performance parameters namely, transconductance generation factor, unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by ~9.67% and ~19.9%, respectively whereas the transconductance generation factor remains almost unaffected. Furthermore, to ensure the device capability in circuit application a CMOS inverter and common-source amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based common-source amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.

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