Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Wakabayashi, A.; Mitani, Y.; Horio, K.

doi:10.1109/16.974746

Cited by 13 publications

(2 citation statements)

References 18 publications

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“…Basic equations are Poisson's equation, continuity equations for electrons and holes, which include carrier loss rates via the deep levels and a carrier generation rate by impact ionization, and rate equations for the deep levels. 10,[20][21][22][23][24] The carrier generation rate is expressed as…”

Section: Physical Modelmentioning

confidence: 99%

Analysis of high-kpassivation-layer effects on buffer-related breakdown and current collapse in AlGaN/GaN HEMTs

Satoh

Hanawa

Nakajima

et al. 2015

Jpn. J. Appl. Phys.

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We analyze breakdown characteristics and current collapse in AlGaN/GaN HEMTs, with the passivation layer's relative permittivity ε r as a parameter. It is shown that the off-state breakdown voltage is considerably enhanced by introducing a high-k passivation layer because the electric field at the drain edge of the gate is weakened and the buffer leakage current is reduced. The breakdown voltage in the high-ε r region increases when the gate voltage is changed from %8 to %10 V, because the buffer leakage current is reduced. It is also shown that drain lag and current collapse in AlGaN/GaN HEMTs could be reduced by introducing a high-k thick passivation layer, because the electric field at the drain edge of the gate is reduced, leading to less electron injection into the buffer layer and weaker buffer trapping effects.

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Section: Physical Modelmentioning

confidence: 99%

Analysis of high-kpassivation-layer effects on buffer-related breakdown and current collapse in AlGaN/GaN HEMTs

Satoh

Hanawa

Nakajima

et al. 2015

Jpn. J. Appl. Phys.

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“…In principle, the doped concentration of LDD is less than that of the source/drain (S/D) implants by, at least, 1 order. In the submicron or nano-scale process, the shallow-junction and silicide processes (11) have been adopted to prevent a short channel effect (SCE) (9) and high channel or source/drain (S/D) resistance (10). However, the size of the LDD profile decreased as did its resistance compared that with the inversion channel resistance.…”

Section: Hot Carrier Effectmentioning

confidence: 99%

Extra-Inversion Charge Enhancing Substrate Current During Increased Substrate Bias in 90 nm Process

Wang

Hsieh

et al. 2008

ECS Trans.

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Substrate current ISUB depends on source/drain voltage VDS, and can be used as an index of the hot carrier effect (HCE). Normally, substrate bias influences device performance and other parameters, such as the threshold voltage. On the other hand, the substrate biasing circuit benefits turn-on current and restrains the turn-off current. However, few studies assessed the change to substrate current when forcing different drain voltages and substrate biases. Furthermore, a unique phenomenon was observed: separate and consentient trends existed while gate voltage VGS increased from 0 to 1.8 V and a turning point locates around at the peak value of ISUB. Here, this study identifies the increase in surface inversion charge Qi from substrate effect in weak inversion layer more than in strong one; is correlated with this interesting symptom. In this study, gate length LG of a measured n-channel metal-oxide-semiconductor field effect transistor (nMOSFET) device is 0.18 μm with a 90 nm process.

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High performance GaAs MESFETs with molecular implanted and optimized lowly-doped drain structure for maximized speed, gain and breakdown performance

Wohlmuth¹,

Davenport²,

Bowman³

et al. 2005

Solid-State Electronics

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Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Cited by 13 publications

References 18 publications

Analysis of high-kpassivation-layer effects on buffer-related breakdown and current collapse in AlGaN/GaN HEMTs

Analysis of high-kpassivation-layer effects on buffer-related breakdown and current collapse in AlGaN/GaN HEMTs

Extra-Inversion Charge Enhancing Substrate Current During Increased Substrate Bias in 90 nm Process

High performance GaAs MESFETs with molecular implanted and optimized lowly-doped drain structure for maximized speed, gain and breakdown performance

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