Extra-Inversion Charge Enhancing Substrate Current During Increased Substrate Bias in 90 nm Process

Abstract

Substrate current ISUB depends on source/drain voltage VDS, and can be used as an index of the hot carrier effect (HCE). Normally, substrate bias influences device performance and other parameters, such as the threshold voltage. On the other hand, the substrate biasing circuit benefits turn-on current and restrains the turn-off current. However, few studies assessed the change to substrate current when forcing different drain voltages and substrate biases. Furthermore, a unique phenomenon was observed: separate and consentient trends existed while gate voltage VGS increased from 0 to 1.8 V and a turning point locates around at the peak value of ISUB. Here, this study identifies the increase in surface inversion charge Qi from substrate effect in weak inversion layer more than in strong one; is correlated with this interesting symptom. In this study, gate length LG of a measured n-channel metal-oxide-semiconductor field effect transistor (nMOSFET) device is 0.18 μm with a 90 nm process.