Analysis of electrically biased paramagnetic defect centers in HfO2 and HfxSi1−xO2/(100)Si interfaces

Abstract

This study reports on the first experimental observations of electrically biased paramagnetic defects at 800 °C N2 annealed HfxSi1−xO2 (x=0.4, and 0.6)/(100)Si and HfO2/(100)Si interfaces in metal oxide silicon structures. These defects are examined by electrical-field controlled electron spin resonance (ESR) and correlated with capacitance-voltage (C-V) analysis. Distributions of ESR measured density of interface traps (ESR-Dit), Pb0 and Pb1, exhibit distinct charge humps and peaks in the Si bandgap with maximum defect density of 0.9–1.9×1012 cm−2 eV−1 in the Hf0.4Si0.6O2/Si interface. Three Pb0 and one Pb1 charged ESR-Dit peaks with density of 1.7–2.8×1012 cm−2 eV−1 are observed in the Hf0.6Si0.4O2/Si interface. Cross-sectional transmission electron microscopic images show decreasing interfacial layer (IL) thickness with increasing hafnium composition (x) at the HfxSi1−xO2/Si interface. The roughest IL observed at the HfO2/Si interface may have contributed to an ESR-Dit of Pb0 greater than 2×1013 cm−2 eV−1 and a pinned Fermi level near the midgap. It appears that the energy distributions of interface defects in HfxSi1−xO2/Si and HfO2/Si have different signatures compared to those at SiO2/Si interface, especially the charged peak near the midgap.

Reliability of HfAlO<inf>x</inf> in multi layered gate stack

“…Also, dielectrics with 20 Cy HfAlO x (A 2 ) annealed at 680 0 C, 700 0 C, and 800 0 C showed a subsequent increase in the mid-gap D it (Table III), which further confirms the fact that excess Al presence at Si/SiO 2 interface is detrimental as it contributes to a reduction in the carrier mobility. On the other hand, A 3 showed comparatively higher dielectric thickness due to less crystallization (Table I) and hence, showed a comparable D it value with the control device [21].…”

“…Furthermore, the understanding of interface state degradation under electrical stress can benefit the integration of Al-doped HfO 2 into future CMOS technology. Additionally, since the standard thermal process required for source/drain activation in CMOS devices can be as high as 1000 0 C [21], post deposition annealing (PDA) temperature variation can, therefore, impact the dielectric.…”

Multilayered ALD HfAlO_x and HfO₂ for High-Quality Gate Stacks

“…This further confirms the fact that the presence of excess Al at Si/SiO 2 interface is detrimental. On the other hand, sample A 3 showed comparatively a higher dielectric thickness due to less crystallization (Table I), and hence, showed a comparable D it value with the control device [21]. Fig.…”

“…Additionally, the understanding of interface state degradation under electrical stress can benefit the integration of Al-doped HfO 2 into future CMOS technology. Since the standard thermal process required for source/drain activation can be as high as 1000 • C [21], post deposition annealing (PDA) temperature variation can, therefore, impact the dielectric characteristics.…”

Post Plasma Oxidation Processed ALD Al2O3/Hf1-xZrxO2Thin Films on Ge Substrates: Reliability

“…It is known that the reduction in film thickness slightly increases the interface state density because of increased stress on the interface. 30 Since the combination of Zr addition and SPAO oxidation help better film densification, which resulted in EOT downscaling (Fig. 6a) for devices with more Zr in Hf 1-x Zr x O 2 .…”