Analysis of buffer‐trapping effects on current collapse of GaN FETs

Abstract

PACS 71.55. Eq, 72.20.Jv, 85.30.De, 85.30.Tv Two-dimensional transient simulation of GaN MESFETs is performed in which a deep donor and a deep acceptor in a semi-insulating buffer layer are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that the current collapse is more pronounced when the deep-acceptor density in the buffer layer is higher and when an offstate drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded. . This is called drain lag or gate lag, and is problematic for circuit applications. The slow transients mean that the dc I-V curves and RF I-V curves become quite different, resulting in lower RF power available than that expected from the dc operation. This is called power slump or current collapse in the GaN device field. The current reduction is also referred to as current slump, current compression and RF dispersion. These are serious problems, and there are many experimental works reported on these phenomena [1][2][3][4][5]. But, only a few theoretical works have been reported recently for , although several numerical analyses were made for GaAsbased FETs [8][9][10][11]. In a previous work [7], we made primary two-dimensional simulation of a GaN MESFET on a semi-insulating buffer layer in which a deep donor and a deep acceptor are considered and showed that the drain lag and the current collapse could be reproduced. In this work, we have made more systematic simulations of GaN MESFETs on the semi-insulating buffer layer and studied how the current collapse is affected by impurity densities in the buffer layer and by an applied drain bias.