Analysis of blocking dynamic circuits

Thorp, T.; Liu, D.; Trivedi, Prasiddh

doi:10.1109/tvlsi.2003.816140

Cited by 11 publications

(5 citation statements)

References 22 publications

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“…The dynamic Nor-Nor PLA consists of blocking dynamic logic [19]. Blocking dynamic circuits require all input signals to settle before the evaluation cycle begins, i.e., the clock must be delayed or "blocked" until all inputs are stable.…”

Section: The Base Pla Structurementioning

confidence: 99%

“…The latch capturing D 3h has signals Q 1h and Q 2h . We use a timing notation loosely based on the notation in [19] to formally represent the timing constraints. Within the timing constraint equations we denote the moment in time when a signal rises by the signal name mnemonic, e.g., φ1 , while the falling edge is denoted by the signal mnemonic with an overbar, e.g., φ 1 .…”

Section: Timing Constraintsmentioning

confidence: 99%

“…The notation for dynamic blocking circuits used in[19] uses separate variables for setup time and timing margin. We combine these to variables in Ts because our tuning method does not require differentiating between the two.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Structured and tuned array generation (STAG) for high-performance random logic

Ziegler

Ditlow

Kosonocky

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG's ability for fast turnaround time as well as for high performance and timing critical random logic.

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Section: The Base Pla Structurementioning

confidence: 99%

Section: Timing Constraintsmentioning

confidence: 99%

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Structured and tuned array generation (STAG) for high-performance random logic

Ziegler

Ditlow

Kosonocky

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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“…Buffer is essential to drive the output of domino circuit into the next stage [6,7]. Static CMOS logic circuit consumes power during the toggling of the output state.…”

Section: Introductionmentioning

confidence: 99%

Static Switching Dynamic Buffer Circuit

Pandey

Mishra

Nagaria

2013

Journal of Engineering

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We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

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“…Buffer is essential to drive the output of domino circuit into the next stage [5]. Static CMOS logic circuit consumes power during the toggling of the output state.…”

Section: Introductionmentioning

confidence: 99%

Conditional Precharge Dynamic Buffer Circuit

Pandey¹,

Mishra²,

Mishra³

et al. 2012

IJCA

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In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuit and compared the results with existing circuits for different logic function, loading condition, clock frequency, temperature and power supply. For capacitance 500fF, our proposed circuit reduces power consumption by 72.69%, 26.35% and 24.03% as compared to standard footless domino, SP-Domino and SSPD techniques.

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Analysis of blocking dynamic circuits

Cited by 11 publications

References 22 publications

Structured and tuned array generation (STAG) for high-performance random logic

Structured and tuned array generation (STAG) for high-performance random logic

Static Switching Dynamic Buffer Circuit

Conditional Precharge Dynamic Buffer Circuit

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