Analysis of a hybrid PWM based on modified space vector and triangle comparison methods

Abstract-The line current ripple and the size of the dc-link capacitor can be reduced by interleaving the carriers of the parallel Voltage Source Converters (VSCs). However, the interleaving of carriers introduces circulating current between VSCs, and it should be suppressed. To limit the circulating current, magnetic coupling between the interleaved legs is provided by means of the Coupled Inductor (CI). The design of CI is strongly influenced by the pulsewidth modulation (PWM) scheme used. The analytical model to evaluate the flux-linkage in CI is presented in this paper. The maximum flux density and the core losses being the most important parameters for CI design, they are evaluated for continuous PWM and discontinuous pulsewidth modulation (DPWM) schemes. The effect of each of these PWM schemes on the design of the CI is discussed in the detail. The simulation and experimental results are finally presented to validate the analysis.

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“…Different modulation possibilities exist with variation in the parameter K z [12]. K z = 0.5 results into a classical center aligned SVM.…”

Section: Pulsewidth Modulation Schemes and Their Effect On The Cmentioning

confidence: 99%

“…Similarly, DPWM sequences can be generated by choosing the appropriate value of K z . The SVM, DPWM1 (60 • clamp), DPWM2 and DPWM3 (30 • ) clamp are considered for comparison [12]- [14] and discussed in following subsections.…”

Section: Pulsewidth Modulation Schemes and Their Effect On The Cmentioning

confidence: 99%

Parallel interleaved VSCs: Influence of the PWM scheme on the design of the coupled inductor

Gohil

Bede

Maheshwari

et al. 2014

IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society

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“…However, by increasing the number of levels, SVPWM faces the problem of more complex computations as compared to carrier-based PWM. Therefor many efforts have been made to achieve the SVPWM's performance by using zero-sequence voltage injection in carrier-based PWM [12]- [16]. Relationship between space vector and phase disposition carrier modulation is presented in [17] for hybrid and diode clamped multilevel inverters.…”

Section: Introductionmentioning

confidence: 99%

A Survey on Space-Vector Pulse Width Modulation for Multilevel Inverters

Qamar

Wang

2017

CPSS TPEA

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Abstract-The selection of an appropriate modulation scheme plays a vital role to assure the performance of multilevel inverters. Space vector pulse width modulation (SVPWM) is more efficient among all other pulse width modulation (PWM) techniques due to its key characteristics like better DC voltage utilization, switching losses reduction and easiness in digital implementation. The conventional SVPWM scheme presents some computational complexities due to redundant switching states and large number of space vectors. This paper summarizes five different SVPWM techniques for multilevel inverters which are α-β frame, g-h frame, K-L frame, α'-β' frame and SVPWM based on imaginary coordinate system. g-h frame and K-L frame are based on 60° and 120° coordinates system respectively. To compare the result of these SVPWM schemes, the complex calculations of conventional SVP-WM are converted into simplified line voltages form. The comparison results validate all the SVPWM techniques, but the SVPWM based on imaginary coordinate is found more simple in duty ratio calculations, easier to understand and provides a better control for zero-sequence component for any level of inverter.Index Terms-g-h frame, imaginary coordinate system, K-L frame, multilevel inverters, space vector pulse width modulation (SVPWM), α'-β' frame. I. IntroductIonN OWADAYS, the extensive use of multilevel inverters in high power and high voltage applications has made it a point of attraction for the researchers because of their remarkable performance. As compared with two-level inverters, multilevel inverters have various advantages, e.g. less harmonics in output current and voltages, reduced voltage stress across switching devices, lower dv/dt, better output wave form quality and lower common mode voltages [1], [2]. The diode-clamped 3 level neutral-point clamped (NPC) topology, as shown in Fig. 1 has been the most widely used one among all multilevel inverter topologies that have been proposed in literature [3]- [5].By using an appropriate PWM technique, from discrete voltage levels, multilevel inverters generate the sinusoidal output voltages of different frequencies. Multilevel inverter's output performance depends on modulation algorithm and various PWM algorithms have been developed so far to fulfill the following objectives: less total harmonic distortion (THD), wider linear modulation range, lower switching losses and easy implementation. Among these, the two most popular PWM generation algorithms for multilevel inverters are sinusoidal carrier-based PWM (SPWM) and space vector PWM (SVPWM). In engineering applications, SPWM algorithms maintained their credibility for a long period [6]-[10] but with the development of microcontrollers, SVPWM took place due to its easy digital implementation, better harmonics performance, high DC voltage utilization ratio, reduced switching losses and convenience for capacitor voltage balancing. Moreover, the SVPWM has 15% higher linear modulation range than that of SPWM [11]. However, by increasing the number of...

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“…By changing K o from zero to one, the duration of V 7 application can be changed from 0% to 100% of the combined application time for zero-state vectors. A correlation between the modified space-vector and triangle-comparison methods (with added zero sequence) was established [8].Celanovic introduced a new and computationally efficient space vector modulation (SVM) algorithm for general n-level converters. This algorithm can be implemented on nearly any commercially available digital signal processor and is suited for execution in real time; however, this method is more complex than others [9].Seo proposed a simplified SVPWM method for a three-level inverter.…”

Section: Introductionmentioning

confidence: 99%

Optimized Space Vector Pulse-width Modulation Technique for a Five-level Cascaded H-Bridge Inverter

Matsa¹,

Ahmed²,

Chaudhari³

2014

Journal of Power Electronics

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This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

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Analysis of a hybrid PWM based on modified space vector and triangle comparison methods

Cited by 202 publications

References 11 publications

Parallel interleaved VSCs: Influence of the PWM scheme on the design of the coupled inductor

Parallel interleaved VSCs: Influence of the PWM scheme on the design of the coupled inductor

A Survey on Space-Vector Pulse Width Modulation for Multilevel Inverters

Optimized Space Vector Pulse-width Modulation Technique for a Five-level Cascaded H-Bridge Inverter

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