Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

Sharaf, K.; Elmasry, M.I.

doi:10.1109/4.487997

Cited by 22 publications

(13 citation statements)

References 6 publications

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“…U NTIL now, a few papers dealing with the optimization of the bias current in some specific current-mode logic (CML) gates to maximize the speed performance have been published [1]- [3]. Moreover, only in [4] and [5] general techniques to manage the power-delay trade-off in single CML gates are analyzed and developed, at the best of the authors' knowledge.…”

Section: Introductionmentioning

confidence: 99%

Design strategies of cascaded CML gates

Alioto

Palumbo

2006

IEEE Trans. Circuits Syst. II

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In this paper, a strategy to design paths consisting of cascaded bipolar current-mode logic gates is proposed. In particular, explicit design criteria are derived both for low-power noncritical paths and high-speed critical paths. The analytical results are simple to be applied to actual circuits avoiding the usual timeconsuming approach based on iterative simulations with a trialand-error procedure. Moreover, it provides the designer with a deeper understanding of the power-delay trade-off. Design examples based on a 20-GHz bipolar process are introduced to validate the procedure and clarify its application.Index Terms-Bipolar digital integrated circuits, current mode logic (CML), design methodology, digital circuits, digital integrated circuits, high-speed integrated circuits, integrated circuit design.

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Section: Introductionmentioning

confidence: 99%

Design strategies of cascaded CML gates

Alioto

Palumbo

2006

IEEE Trans. Circuits Syst. II

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“…It is worth noting that, after setting the logic swing from considerations at the system level, coefficients (8) are constant during the design. Relationship (7) expresses in a closed form the delay dependence on the the bias current ISS, i.e.…”

Section: Il Approximate Circuit Analysismentioning

confidence: 99%

“…Numerical values of coefficients in (8) are reported in Table 11. By inspection of Table 1, assumptions introduced to simplify the transit time dependence on process parameters are largely satisfied (i.e.…”

Section: Il Approximate Circuit Analysismentioning

confidence: 99%

A delay model of CML gates valid under high-current effects

Alioto

Palumbo

2003 46th Midwest Symposium on Circuits and Systems

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In this paper a delay model ofbipolar CML gates which extends that in [I 1] for a wide range ofbias currents is proposed. In particular, it accounts for high-current effects, i.e. the degradation in the transit time.The model proposed is derivedfrom an approximate circuit analysis and has a simple compact expression as a function of the bias current, that makes it suitable for fast timing analysis or automatic bias current optimization.Simulation of CML circuits with a 20-GHz bipolar process shows that the model has a good accuracy in a wide range ofcurrent and loading conditions.

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“…Actual CML circuits are made up of cascaded gates, thus results in [7]- [11] cannot immediately applied to practical design. Moreover, due to the high complexity of typical circuits, the design procedure based on iterated simulations (with a trial-and-error approach or resorting to an Optimizer CAD tool) is unfeasible, since it is very time consuming and requires a very high computational effort.…”

Section: Introductionmentioning

confidence: 98%

“…Until now, the optimization of the bias current of a single CML gate has been addressed in a few papers for some specific topologies (e.g. inverter, XOR gate) [7]- [11]. At the best of the authors' knowledge, general techniques to manage the power-delay trade-off in single CML gates are developed only in [10]- [11].…”

Section: Introductionmentioning

confidence: 99%