Design strategies of cascaded CML gates

Abstract

In this paper, a strategy to design paths consisting of cascaded bipolar current-mode logic gates is proposed. In particular, explicit design criteria are derived both for low-power noncritical paths and high-speed critical paths. The analytical results are simple to be applied to actual circuits avoiding the usual timeconsuming approach based on iterative simulations with a trialand-error procedure. Moreover, it provides the designer with a deeper understanding of the power-delay trade-off. Design examples based on a 20-GHz bipolar process are introduced to validate the procedure and clarify its application.Index Terms-Bipolar digital integrated circuits, current mode logic (CML), design methodology, digital circuits, digital integrated circuits, high-speed integrated circuits, integrated circuit design.

Simple and Accurate Model for the Propagation Delay in MCML Gates

“…Since the late 1990s and up to recent years, several digital gate models have been developed based on the small-signal representation of the transistor with an improved modeling of its parasitic capacitors, suitable for large signal swings. Such models covered both CML [10][11][12] and MCML gates [13][14][15][16]; they were proficiently used to optimize the design of standard CML and MCML gates [17][18][19][20], and, recently, were also used for advanced gates developed for very low-voltage environments [21][22][23][24].…”