Abstract:This paper describes the architecture and operating principles of two digital pulse-width modulator (DPWM) implementations for low-cost field-programmable gate arrays (FPGAs). Both architectures are based on a countercomparator block to process the most significant bits (MSB) portion of the reference input, enriched with additional elements to enhance duty-cycle resolution according to the less significant bits (LSB). The first architecture described has already been reported, it uses the on-chip PLL blocks to… Show more
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